[PATCH 07/18] drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx at lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 07/18] drm/amdgpu: abstract disable identity aperture for
> gfxhub/mmhub
> 
> Signed-off-by: Huang Rui <ray.huang at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 37 ++++++++++++++++++-
> -------------
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 36 +++++++++++++++++-
> -------------
>  2 files changed, 41 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index fbabd11..5fdc9be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -167,6 +167,26 @@ static void
> gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
>  	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL),
> tmp);
>  }
> 
> +static void gfxhub_v1_0_dis_identity_aperture(struct amdgpu_device
> *adev)

Call this function gfxhub_v1_0_disable_identity_aperture() for consistency with the other newly abstracted functions.  Same for mmhub.

Alex

> +{
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> +	       0XFFFFFFFF);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +
> +}
> +
>  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -193,22 +213,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
>  	gfxhub_v1_0_init_cache_regs(adev);
> 
>  	gfxhub_v1_0_enable_system_domain(adev);
> -
> -	/* Disable identity aperture.*/
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> 0XFFFFFFFF);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +	gfxhub_v1_0_dis_identity_aperture(adev);
> 
>  	for (i = 0; i <= 14; i++) {
>  		tmp = RREG32(SOC15_REG_OFFSET(GC, 0,
> mmVM_CONTEXT1_CNTL) + i);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 888ce7f..84148578 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -180,6 +180,25 @@ static void
> mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> mmVM_CONTEXT0_CNTL), tmp);
>  }
> 
> +static void mmhub_v1_0_dis_identity_aperture(struct amdgpu_device
> *adev)
> +{
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> +	       0XFFFFFFFF);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +}
> +
>  int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -206,22 +225,7 @@ int mmhub_v1_0_gart_enable(struct
> amdgpu_device *adev)
>  	mmhub_v1_0_init_cache_regs(adev);
> 
>  	mmhub_v1_0_enable_system_domain(adev);
> -
> -	/* Disable identity aperture.*/
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> 0XFFFFFFFF);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +	mmhub_v1_0_dis_identity_aperture(adev);
> 
>  	for (i = 0; i <= 14; i++) {
>  		tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0,
> mmVM_CONTEXT1_CNTL)
> --
> 2.7.4
> 
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