[PATCH 2/2] drm/amdkfd: Use order_base_2 to get log2 of buffes sizes

[Oded Gabbay]

Thanks,
Applied to -next

On Tue, Nov 7, 2017 at 12:04 AM, Deucher, Alexander
<Alexander.Deucher at amd.com> wrote:
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
>> Of Felix Kuehling
>> Sent: Monday, November 06, 2017 2:52 PM
>> To: amd-gfx at lists.freedesktop.org; oded.gabbay at gmail.com
>> Cc: Kuehling, Felix
>> Subject: [PATCH 2/2] drm/amdkfd: Use order_base_2 to get log2 of buffes
>> sizes
>>
>> Replace (ffs(size) - 1) with order_base_2(size) as a more straight
>> forward way to get log2 of buffer sizes.
>>
>> Signed-off-by: Felix Kuehling <Felix.Kuehling at amd.com>
>
> Series is:
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 6 +++---
>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 6 +++---
>>  2 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> index efed6ef..7aa57ab 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> @@ -183,7 +183,7 @@ static int update_mqd(struct mqd_manager *mm,
>> void *mqd,
>>        * Calculating queue size which is log base 2 of actual queue size -1
>>        * dwords and another -1 for ffs
>>        */
>> -     m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
>> +     m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>>       m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q-
>> >read_ptr);
>> @@ -208,7 +208,7 @@ static int update_mqd_sdma(struct mqd_manager
>> *mm, void *mqd,
>>       struct cik_sdma_rlc_registers *m;
>>
>>       m = get_sdma_mqd(mqd);
>> -     m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1)
>> +     m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
>>                       << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>>                       q->vmid <<
>> SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>>                       1 <<
>> SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
>> @@ -349,7 +349,7 @@ static int update_mqd_hiq(struct mqd_manager
>> *mm, void *mqd,
>>        * Calculating queue size which is log base 2 of actual queue
>>        * size -1 dwords
>>        */
>> -     m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
>> +     m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>>       m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q-
>> >read_ptr);
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> index 85e1b67..2ba7cea 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> @@ -121,7 +121,7 @@ static int __update_mqd(struct mqd_manager *mm,
>> void *mqd,
>>       m->cp_hqd_pq_control = 5 <<
>> CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
>>                       atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT
>> |
>>                       mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
>> -     m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
>> +     m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>>       pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
>>
>>       m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
>> >queue_address >> 8);
>> @@ -151,7 +151,7 @@ static int __update_mqd(struct mqd_manager *mm,
>> void *mqd,
>>        * is safe, giving a maximum field value of 0xA.
>>        */
>>       m->cp_hqd_eop_control |= min(0xA,
>> -             ffs(q->eop_ring_buffer_size / 4) - 1 - 1);
>> +             order_base_2(q->eop_ring_buffer_size / 4) - 1);
>>       m->cp_hqd_eop_base_addr_lo =
>>                       lower_32_bits(q->eop_ring_buffer_address >> 8);
>>       m->cp_hqd_eop_base_addr_hi =
>> @@ -287,7 +287,7 @@ static int update_mqd_sdma(struct mqd_manager
>> *mm, void *mqd,
>>       struct vi_sdma_mqd *m;
>>
>>       m = get_sdma_mqd(mqd);
>> -     m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1)
>> +     m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
>>               << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>>               q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>>               1 <<
>> SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
>> --
>> 2.7.4
>>
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