[Resend 1/3] drm/amd/include:cleanup vega10 sdma0/1 header files.

Christian König christian.koenig at amd.com
Fri Nov 17 10:34:23 UTC 2017


Am 17.11.2017 um 11:27 schrieb Feifei Xu:
> To remove include/asic_reg/vega10 folder,create IP folders sdma0/1.
> This patch cleanup asic_reg/vega10/SDMA folders.
>
> Change-Id: I861f4047cb23154f9094553b602157b01da9028e
> Signed-off-by: Feifei Xu <Feifei.Xu at amd.com>

Not sure if we should distinct between sdma0/sdma1, but in general looks 
like a good idea to me.

Series is Acked-by: Christian König <christian.koenig at amd.com>.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c                 | 8 ++++----
>   drivers/gpu/drm/amd/amdgpu/psp_v3_1.c                             | 2 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c                            | 8 ++++----
>   drivers/gpu/drm/amd/amdgpu/soc15.c                                | 4 ++--
>   drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c          | 2 +-
>   drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c                   | 2 +-
>   .../include/asic_reg/{vega10/SDMA0 => sdma0}/sdma0_4_0_default.h  | 0
>   .../include/asic_reg/{vega10/SDMA0 => sdma0}/sdma0_4_0_offset.h   | 0
>   .../include/asic_reg/{vega10/SDMA0 => sdma0}/sdma0_4_0_sh_mask.h  | 0
>   .../include/asic_reg/{vega10/SDMA1 => sdma1}/sdma1_4_0_default.h  | 0
>   .../include/asic_reg/{vega10/SDMA1 => sdma1}/sdma1_4_0_offset.h   | 0
>   .../include/asic_reg/{vega10/SDMA1 => sdma1}/sdma1_4_0_sh_mask.h  | 0
>   12 files changed, 13 insertions(+), 13 deletions(-)
>   rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SDMA0 => sdma0}/sdma0_4_0_default.h (100%)
>   rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SDMA0 => sdma0}/sdma0_4_0_offset.h (100%)
>   rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SDMA0 => sdma0}/sdma0_4_0_sh_mask.h (100%)
>   rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SDMA1 => sdma1}/sdma1_4_0_default.h (100%)
>   rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SDMA1 => sdma1}/sdma1_4_0_offset.h (100%)
>   rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SDMA1 => sdma1}/sdma1_4_0_sh_mask.h (100%)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> index d5b430d..0df691d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> @@ -35,10 +35,10 @@
>   #include "vega10/GC/gc_9_0_offset.h"
>   #include "vega10/GC/gc_9_0_sh_mask.h"
>   #include "vega10/vega10_enum.h"
> -#include "vega10/SDMA0/sdma0_4_0_offset.h"
> -#include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
> -#include "vega10/SDMA1/sdma1_4_0_offset.h"
> -#include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
> +#include "sdma0/sdma0_4_0_offset.h"
> +#include "sdma0/sdma0_4_0_sh_mask.h"
> +#include "sdma1/sdma1_4_0_offset.h"
> +#include "sdma1/sdma1_4_0_sh_mask.h"
>   #include "vega10/ATHUB/athub_1_0_offset.h"
>   #include "vega10/ATHUB/athub_1_0_sh_mask.h"
>   #include "vega10/OSSSYS/osssys_4_0_offset.h"
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index c7bcfe8..b855964 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -35,7 +35,7 @@
>   #include "vega10/MP/mp_9_0_offset.h"
>   #include "vega10/MP/mp_9_0_sh_mask.h"
>   #include "vega10/GC/gc_9_0_offset.h"
> -#include "vega10/SDMA0/sdma0_4_0_offset.h"
> +#include "sdma0/sdma0_4_0_offset.h"
>   #include "vega10/NBIO/nbio_6_1_offset.h"
>   
>   MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index fe78c00..3f68638 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -28,10 +28,10 @@
>   #include "amdgpu_trace.h"
>   
>   #include "vega10/soc15ip.h"
> -#include "vega10/SDMA0/sdma0_4_0_offset.h"
> -#include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
> -#include "vega10/SDMA1/sdma1_4_0_offset.h"
> -#include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
> +#include "sdma0/sdma0_4_0_offset.h"
> +#include "sdma0/sdma0_4_0_sh_mask.h"
> +#include "sdma1/sdma1_4_0_offset.h"
> +#include "sdma1/sdma1_4_0_sh_mask.h"
>   #include "vega10/MMHUB/mmhub_1_0_offset.h"
>   #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
>   #include "vega10/HDP/hdp_4_0_offset.h"
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 4e67fe1..367d579 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -38,8 +38,8 @@
>   #include "vega10/UVD/uvd_7_0_offset.h"
>   #include "vega10/GC/gc_9_0_offset.h"
>   #include "vega10/GC/gc_9_0_sh_mask.h"
> -#include "vega10/SDMA0/sdma0_4_0_offset.h"
> -#include "vega10/SDMA1/sdma1_4_0_offset.h"
> +#include "sdma0/sdma0_4_0_offset.h"
> +#include "sdma1/sdma1_4_0_offset.h"
>   #include "vega10/HDP/hdp_4_0_offset.h"
>   #include "vega10/HDP/hdp_4_0_sh_mask.h"
>   #include "vega10/MP/mp_9_0_offset.h"
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> index cfc5d70..f7fe2a4 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> @@ -25,7 +25,7 @@
>   #include "vega10/vega10_enum.h"
>   #include "vega10/GC/gc_9_0_offset.h"
>   #include "vega10/GC/gc_9_0_sh_mask.h"
> -#include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
> +#include "sdma0/sdma0_4_0_sh_mask.h"
>   
>   static int update_qpd_v9(struct device_queue_manager *dqm,
>   			 struct qcm_process_device *qpd);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> index fa4bc43..953f252 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> @@ -29,7 +29,7 @@
>   #include "v9_structs.h"
>   #include "vega10/GC/gc_9_0_offset.h"
>   #include "vega10/GC/gc_9_0_sh_mask.h"
> -#include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
> +#include "sdma0/sdma0_4_0_sh_mask.h"
>   
>   static inline struct v9_mqd *get_mqd(void *mqd)
>   {
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
> similarity index 100%
> rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
> rename to drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h
> similarity index 100%
> rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
> rename to drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h
> similarity index 100%
> rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
> rename to drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
> similarity index 100%
> rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
> rename to drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h
> similarity index 100%
> rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
> rename to drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h
> similarity index 100%
> rename from drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
> rename to drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h




More information about the amd-gfx mailing list