[PATCH] drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)

Christian K├Ânig ckoenig.leichtzumerken at gmail.com
Tue Nov 21 14:45:00 UTC 2017


Am 21.11.2017 um 11:23 schrieb Frank Min:
> 1. program vce 4.0 fw with 48 bit address
> 2. correct vce 4.0 fw stack and date offset
>
> Change-Id: I835f3f52f3b29f996812a3948aabede9f2d9b056
> Signed-off-by: Frank Min <Frank.Min at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 97 ++++++++++++++++++++++-------------
>   1 file changed, 62 insertions(+), 35 deletions(-)
>   mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> old mode 100644
> new mode 100755
> index 7574554..dc7b615
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -243,59 +243,86 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
>   
>   		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> -						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> -						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
>   						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
> +						(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff);
>   		} else {
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
>   						adev->vce.gpu_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
> +						(adev->vce.gpu_addr >> 40) & 0xff);
> +		}
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
>   						adev->vce.gpu_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_64BIT_BAR1),
> +						(adev->vce.gpu_addr >> 40) & 0xff);
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
>   						adev->vce.gpu_addr >> 8);
> -		}
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +						mmVCE_LMI_VCPU_CACHE_64BIT_BAR2),
> +						(adev->vce.gpu_addr >> 40) & 0xff);
>   
>   		offset = AMDGPU_VCE_FIRMWARE_OFFSET;
>   		size = VCE_V4_0_FW_SIZE;
> -		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
> -					    offset & 0x7FFFFFFF);
> -		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
> -
> -		offset += size;
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_VCPU_CACHE_OFFSET0),
> +					offset & ~0x0f000000);
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_VCPU_CACHE_SIZE0), size);
> +
> +		offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ?
> +				offset + size : 0;
>   		size = VCE_V4_0_STACK_SIZE;
> -		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),
> -					    offset & 0x7FFFFFFF);
> -		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_VCPU_CACHE_OFFSET1),
> +					(offset & ~0x0f000000) | (1 << 24));

That mask still looks incorrect to me.

> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_VCPU_CACHE_SIZE1), size);
>   
>   		offset += size;
>   		size = VCE_V4_0_DATA_SIZE;
> -		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2),
> -					    offset & 0x7FFFFFFF);
> -		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
> -
> -		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);
> -		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),
> -						   VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
> -						   VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_VCPU_CACHE_OFFSET2),
> +					(offset & ~0x0f000000) | (2 << 24));

Dito.

> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_VCPU_CACHE_SIZE2), size);
> +
> +		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_LMI_CTRL2), ~0x100, 0);
> +		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_SYS_INT_EN),
> +					VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
> +					VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
>   
>   		/* end of MC_RESUME */
> -		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
> -						   VCE_STATUS__JOB_BUSY_MASK, ~VCE_STATUS__JOB_BUSY_MASK);
> -		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),
> -						   ~0x200001, VCE_VCPU_CNTL__CLK_EN_MASK);
> -		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
> -						   ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 0);
> +		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_STATUS),
> +					VCE_STATUS__JOB_BUSY_MASK,
> +					~VCE_STATUS__JOB_BUSY_MASK);
> +		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_VCPU_CNTL),
> +					~0x200001,
> +					VCE_VCPU_CNTL__CLK_EN_MASK);
> +		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_SOFT_RESET),
> +					~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 0);

Unrelated coding style change, please concentrate on the functional 
change for this patch.

>   
>   		MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
> -					      VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK,
> -					      VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK);
> +					VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK,
> +					VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK);

Here the indentation is wrong. Looks like it was correct before the change.

Regards,
Christian.

>   
>   		/* clear BUSY flag */
> -		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
> -						   ~VCE_STATUS__JOB_BUSY_MASK, 0);
> +		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0,
> +					mmVCE_STATUS),
> +					~VCE_STATUS__JOB_BUSY_MASK, 0);
>   
>   		/* add end packet */
>   		memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));




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