FW: [PATCH] drm/amd/vce: correct vce fw data and stack size config for sriov

[Christian König]

> 1）the coding style is correct on the patch itself but looks incorrect in mail
I use a Thunderbird plugin to show the code as it would apply to the 
file and sorry at least in this version the coding style is completely 
incorrect.

Franks V2 patch looked much better, so I think that was just an issue 
created by forwarding the patch.

> 2) can you point what do you mean on the sentence "programing 0 to register"
That was just me confused because the coding style looked so odd.

But I've already took a look at newer versions of the patch and the 
masks applied to the offsets still looked really strange.

Going to follow up on the newest version of the patch.

Regards,
Christian.

Am 22.11.2017 um 07:30 schrieb Liu, Monk:
> Hi Christian
>
> This patch can fix a VCE world switch hang bug, because couple registers were wrongly programed with the same address so hardware fight with each other
> We have verified this patch,
>
> Regarding your comments：
> 1）the coding style is correct on the patch itself but looks incorrect in mail
> 2) can you point what do you mean on the sentence "programing 0 to register"
>
> Since Frank hasn't applied for the member of amd-gfx, so his patch cannot go to amd-gfx loop directly
>
>
> BR Monk
>
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of Frank Min
> Sent: 2017年11月21日 16:34
> To: amd-gfx at lists.freedesktop.org
> Cc: Min, Frank <Frank.Min at amd.com>
> Subject: [PATCH] drm/amd/vce: correct vce fw data and stack size config for sriov
>
> Signed-off-by: Frank Min <Frank.Min at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 30 +++++++++++++++++-------------
>   1 file changed, 17 insertions(+), 13 deletions(-)  mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> old mode 100644
> new mode 100755
> index 7574554..4a92530
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -243,37 +243,41 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
>   
>   		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> -						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> -						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
>   						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
> +						(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) &
> +0xff);
>   		} else {
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
>   						adev->vce.gpu_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> +			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
> +						(adev->vce.gpu_addr >> 40) & 0xff);
> +		}
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
>   						adev->vce.gpu_addr >> 8);
> -		    MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1),
> +						(adev->vce.gpu_addr >> 40) & 0xff);
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
> +mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
>   						adev->vce.gpu_addr >> 8);
> -		}
> +		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2),
> +						(adev->vce.gpu_addr >> 40) & 0xff);
>   
>   		offset = AMDGPU_VCE_FIRMWARE_OFFSET;
>   		size = VCE_V4_0_FW_SIZE;
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
> -					    offset & 0x7FFFFFFF);
> +					offset & ~0x0f000000);
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
>   
> -		offset += size;
> +		offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset +
> +size : 0;
>   		size = VCE_V4_0_STACK_SIZE;
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),
> -					    offset & 0x7FFFFFFF);
> +					(offset & ~0x0f000000) | (1 << 24));
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
>   
>   		offset += size;
>   		size = VCE_V4_0_DATA_SIZE;
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2),
> -					    offset & 0x7FFFFFFF);
> +					(offset & ~0x0f000000) | (2 << 24));
>   		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
>   
>   		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);
> --
> 1.9.1
>
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