[PATCH 07/16] drm/amd/include:cleanup vega10 dce header files.

Feifei Xu Feifei.Xu at amd.com
Fri Nov 24 06:26:35 UTC 2017


Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h.

Change-Id: I845e6551c6af8c01bf7964641cf89e8aa1658c11
Signed-off-by: Feifei Xu <Feifei.Xu at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c              |    4 +-
 .../amd/display/dc/dce120/dce120_hw_sequencer.c    |    4 +-
 .../drm/amd/display/dc/dce120/dce120_resource.c    |    4 +-
 .../display/dc/dce120/dce120_timing_generator.c    |    4 +-
 .../amd/display/dc/gpio/dce120/hw_factory_dce120.c |    4 +-
 .../display/dc/gpio/dce120/hw_translate_dce120.c   |    4 +-
 .../amd/display/dc/i2caux/dce120/i2caux_dce120.c   |    4 +-
 .../amd/display/dc/irq/dce120/irq_service_dce120.c |    4 +-
 .../asic_reg/{vega10/DC => dce}/dce_12_0_offset.h  |    0
 .../asic_reg/{vega10/DC => dce}/dce_12_0_sh_mask.h |    0
 .../include/asic_reg/vega10/DC/dce_12_0_default.h  | 9868 --------------------
 11 files changed, 16 insertions(+), 9884 deletions(-)
 rename drivers/gpu/drm/amd/include/asic_reg/{vega10/DC => dce}/dce_12_0_offset.h (100%)
 rename drivers/gpu/drm/amd/include/asic_reg/{vega10/DC => dce}/dce_12_0_sh_mask.h (100%)
 delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 141915c..1d5c540 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -29,8 +29,8 @@
 #include "hdp/hdp_4_0_offset.h"
 #include "hdp/hdp_4_0_sh_mask.h"
 #include "vega10/GC/gc_9_0_sh_mask.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/vega10_enum.h"
 #include "vega10/MMHUB/mmhub_1_0_offset.h"
 #include "athub/athub_1_0_offset.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
index 1a0b54d..8613ecf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
@@ -31,8 +31,8 @@
 
 #include "dce110/dce110_hw_sequencer.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 #include "reg_helper.h"
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 5c48c22..e59a4e6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -54,8 +54,8 @@
 #include "dce/dce_abm.h"
 #include "dce/dce_dmcu.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 #include "vega10/NBIO/nbio_6_1_offset.h"
 #include "reg_helper.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 2502182..5ad04d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -25,8 +25,8 @@
 
 #include "dm_services.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 #include "dc_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
index 4ced9a7..d8b70d1 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
@@ -34,8 +34,8 @@
 
 #include "hw_factory_dce120.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 #define block HPD
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
index af3843a..0d0bc44 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
@@ -33,8 +33,8 @@
 #include "include/gpio_types.h"
 #include "../hw_translate.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 /* begin *********************
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
index 668981a..0de5325 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
@@ -36,8 +36,8 @@
 #include "../dce110/aux_engine_dce110.h"
 #include "../dce110/i2caux_dce110.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 /* begin *********************
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
index 2ad56b1..8135d7a 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
@@ -30,8 +30,8 @@
 #include "irq_service_dce120.h"
 #include "../dce110/irq_service_dce110.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 #include "ivsrcid/ivsrcid_vislands30.h"
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
rename to drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
similarity index 100%
rename from drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
rename to drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
deleted file mode 100644
index 8a0007c..0000000
-- 
2.7.4



More information about the amd-gfx mailing list