[PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

Christian K├Ânig ckoenig.leichtzumerken at gmail.com
Wed Nov 29 20:08:00 UTC 2017


Am 29.11.2017 um 20:09 schrieb Shaoyun Liu:
> Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
> Signed-off-by: Shaoyun Liu <Shaoyun.Liu at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c     | 259 +++++++++++++++---------------
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c     |  14 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c    |  13 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c    |  12 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c    |  88 +++++-----
>   drivers/gpu/drm/amd/amdgpu/soc15.c        |  93 ++++++++---
>   drivers/gpu/drm/amd/amdgpu/soc15.h        |   4 +
>   drivers/gpu/drm/amd/amdgpu/soc15_common.h |   3 +
>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c     |   3 +-
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c     |   2 +-
>   10 files changed, 278 insertions(+), 213 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 5497ed6..f0560d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -67,150 +67,151 @@
>   
>   static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
>   {
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
> -	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
> -	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
> +	/* Fix me if GC base for the register is not 0x2000 in the future asic */

Yeah, we need a better solution for this.

How about a VG10_GOLDEN_REG macro or something like this?

Regards,
Christian.

> +	{ (0x2000 + mmGDS_VMID0_BASE),
> +	  (0x2000 + mmGDS_VMID0_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID0),
> +	  (0x2000 + mmGDS_OA_VMID0) },
> +	{ (0x2000 + mmGDS_VMID1_BASE),
> +	  (0x2000 + mmGDS_VMID1_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID1),
> +	  (0x2000 + mmGDS_OA_VMID1) },
> +	{ (0x2000 + mmGDS_VMID2_BASE),
> +	  (0x2000 + mmGDS_VMID2_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID2),
> +	  (0x2000 + mmGDS_OA_VMID2) },
> +	{ (0x2000 + mmGDS_VMID3_BASE),
> +	  (0x2000 + mmGDS_VMID3_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID3),
> +	  (0x2000 + mmGDS_OA_VMID3) },
> +	{ (0x2000 + mmGDS_VMID4_BASE),
> +	  (0x2000 + mmGDS_VMID4_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID4),
> +	  (0x2000 + mmGDS_OA_VMID4) },
> +	{ (0x2000 + mmGDS_VMID5_BASE),
> +	  (0x2000 + mmGDS_VMID5_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID5),
> +	  (0x2000 + mmGDS_OA_VMID5) },
> +	{ (0x2000 + mmGDS_VMID6_BASE),
> +	  (0x2000 + mmGDS_VMID6_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID6),
> +	  (0x2000 + mmGDS_OA_VMID6) },
> +	{ (0x2000 + mmGDS_VMID7_BASE),
> +	  (0x2000 + mmGDS_VMID7_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID7),
> +	  (0x2000 + mmGDS_OA_VMID7) },
> +	{ (0x2000 + mmGDS_VMID8_BASE),
> +	  (0x2000 + mmGDS_VMID8_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID8),
> +	  (0x2000 + mmGDS_OA_VMID8) },
> +	{ (0x2000 + mmGDS_VMID9_BASE),
> +	  (0x2000 + mmGDS_VMID9_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID9),
> +	  (0x2000 + mmGDS_OA_VMID9) },
> +	{ (0x2000 + mmGDS_VMID10_BASE),
> +	  (0x2000 + mmGDS_VMID10_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID10),
> +	  (0x2000 + mmGDS_OA_VMID10) },
> +	{ (0x2000 + mmGDS_VMID11_BASE),
> +	  (0x2000 + mmGDS_VMID11_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID11),
> +	  (0x2000 + mmGDS_OA_VMID11) },
> +	{ (0x2000 + mmGDS_VMID12_BASE),
> +	  (0x2000 + mmGDS_VMID12_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID12),
> +	  (0x2000 + mmGDS_OA_VMID12)},
> +	{ (0x2000 + mmGDS_VMID13_BASE),
> +	  (0x2000 + mmGDS_VMID13_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID13),
> +	  (0x2000 + mmGDS_OA_VMID13) },
> +	{ (0x2000 + mmGDS_VMID14_BASE),
> +	  (0x2000 + mmGDS_VMID14_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID14),
> +	  (0x2000 + mmGDS_OA_VMID14) },
> +	{ (0x2000 + mmGDS_VMID15_BASE),
> +	  (0x2000 + mmGDS_VMID15_SIZE),
> +	  (0x2000 + mmGDS_GWS_VMID15),
> +	  (0x2000 + mmGDS_OA_VMID15) }
>   };
>   
>   static const u32 golden_settings_gc_9_0[] =
>   {
> -	SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
> -	SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
> -	SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
> -	SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
> -	SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
> -	SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
> -	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
> -	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
> -	SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
> -	SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
> -	SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
> +	SOC15_REG_ENTRY(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
> +	SOC15_REG_ENTRY(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
> +	SOC15_REG_ENTRY(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
> +	SOC15_REG_ENTRY(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
> +	SOC15_REG_ENTRY(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
> +	SOC15_REG_ENTRY(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
> +	SOC15_REG_ENTRY(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
> +	SOC15_REG_ENTRY(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
> +	SOC15_REG_ENTRY(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
> +	SOC15_REG_ENTRY(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
> +	SOC15_REG_ENTRY(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
>   };
>   
>   static const u32 golden_settings_gc_9_0_vg10[] =
>   {
> -	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
> -	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
> -	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
> -	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
> -	SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
> -	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
> +	SOC15_REG_ENTRY(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
> +	SOC15_REG_ENTRY(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
> +	SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
> +	SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
> +	SOC15_REG_ENTRY(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
> +	SOC15_REG_ENTRY(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
>   };
>   
>   static const u32 golden_settings_gc_9_1[] =
>   {
> -	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
> -	SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
> -	SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
> -	SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
> -	SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
> -	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
> -	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
> -	SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
> -	SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
> -	SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
> +	SOC15_REG_ENTRY(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
> +	SOC15_REG_ENTRY(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
> +	SOC15_REG_ENTRY(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
> +	SOC15_REG_ENTRY(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
> +	SOC15_REG_ENTRY(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
> +	SOC15_REG_ENTRY(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
> +	SOC15_REG_ENTRY(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
> +	SOC15_REG_ENTRY(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
> +	SOC15_REG_ENTRY(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
> +	SOC15_REG_ENTRY(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
>   };
>   
>   static const u32 golden_settings_gc_9_1_rv1[] =
>   {
> -	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
> -	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
> -	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
> -	SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
> -	SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
> -	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
> +	SOC15_REG_ENTRY(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
> +	SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
> +	SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
> +	SOC15_REG_ENTRY(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
> +	SOC15_REG_ENTRY(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
> +	SOC15_REG_ENTRY(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
>   };
>   
>   static const u32 golden_settings_gc_9_x_common[] =
>   {
> -	SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
> -	SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
> +	SOC15_REG_ENTRY(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
> +	SOC15_REG_ENTRY(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
>   };
>   
>   #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
> @@ -230,18 +231,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
>   {
>   	switch (adev->asic_type) {
>   	case CHIP_VEGA10:
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_gc_9_0,
>   						 ARRAY_SIZE(golden_settings_gc_9_0));
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_gc_9_0_vg10,
>   						 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
>   		break;
>   	case CHIP_RAVEN:
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_gc_9_1,
>   						 ARRAY_SIZE(golden_settings_gc_9_1));
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_gc_9_1_rv1,
>   						 ARRAY_SIZE(golden_settings_gc_9_1_rv1));
>   		break;
> @@ -249,7 +250,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
>   		break;
>   	}
>   
> -	amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
> +	soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
>   					(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 30eb625..ca66e1c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -35,6 +35,7 @@
>   #include "mmhub/mmhub_1_0_offset.h"
>   #include "athub/athub_1_0_offset.h"
>   
> +#include "soc15.h"
>   #include "soc15_common.h"
>   #include "umc/umc_6_0_sh_mask.h"
>   
> @@ -76,14 +77,14 @@
>   
>   static const u32 golden_settings_mmhub_1_0_0[] =
>   {
> -	SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
> -	SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
> +	SOC15_REG_ENTRY(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
> +	SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
>   };
>   
>   static const u32 golden_settings_athub_1_0_0[] =
>   {
> -	SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
> -	SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
> +	SOC15_REG_ENTRY(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
> +	SOC15_REG_ENTRY(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
>   };
>   
>   /* Ecc related register addresses, (BASE + reg offset) */
> @@ -895,12 +896,13 @@ static int gmc_v9_0_sw_fini(void *handle)
>   
>   static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
>   {
> +
>   	switch (adev->asic_type) {
>   	case CHIP_VEGA10:
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						golden_settings_mmhub_1_0_0,
>   						ARRAY_SIZE(golden_settings_mmhub_1_0_0));
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						golden_settings_athub_1_0_0,
>   						ARRAY_SIZE(golden_settings_athub_1_0_0));
>   		break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 76db711..3b87b8a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -78,8 +78,8 @@ u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
>   
>   static const u32 nbio_sdma_doorbell_range_reg[] =
>   {
> -	SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
> -	SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
> +	(0xd20 + mmBIF_SDMA0_DOORBELL_RANGE),
> +	(0xd20 + mmBIF_SDMA1_DOORBELL_RANGE)
>   };
>   
>   void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> @@ -94,6 +94,7 @@ void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
>   		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>   
>   	WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);
> +
>   }
>   
>   void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
> @@ -216,8 +217,8 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
>   }
>   
>   const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
> -	.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ),
> -	.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE),
> +	.hdp_flush_req_offset =  0xd20 + mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ,
> +	.hdp_flush_done_offset = 0xd20 + mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE,
>   	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
>   	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
>   	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
> @@ -233,8 +234,8 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
>   };
>   
>   const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
> -	.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
> -	.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
> +	.index_offset = 0x0 + mmPCIE_INDEX,
> +	.data_offset = 0x0 + mmPCIE_DATA,
>   };
>   
>   void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index 1fb7717..7252d572 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -75,8 +75,8 @@ u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
>   
>   static const u32 nbio_sdma_doorbell_range_reg[] =
>   {
> -	SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
> -	SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
> +	(0xd20 + mmBIF_SDMA0_DOORBELL_RANGE),
> +	(0xd20 + mmBIF_SDMA1_DOORBELL_RANGE)
>   };
>   
>   void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> @@ -186,8 +186,8 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev)
>   }
>   
>   const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
> -	.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ),
> -	.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE),
> +	.hdp_flush_req_offset = 0xd20 + mmGPU_HDP_FLUSH_REQ,
> +	.hdp_flush_done_offset = 0xd20 + mmGPU_HDP_FLUSH_DONE,
>   	.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
>   	.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
>   	.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
> @@ -203,6 +203,6 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev)
>   };
>   
>   const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data = {
> -	.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2),
> -	.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)
> +	.index_offset = 0x0 + mmPCIE_INDEX2,
> +	.data_offset = 0x0 + mmPCIE_DATA2
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index e324c66..c653695 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -54,57 +54,57 @@
>   static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
>   
>   static const u32 golden_settings_sdma_4[] = {
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0
>   };
>   
>   static const u32 golden_settings_sdma_vg10[] = {
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
> -	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
> +	SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
>   };
>   
>   static const u32 golden_settings_sdma_4_1[] =
>   {
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0
>   };
>   
>   static const u32 golden_settings_sdma_rv1[] =
>   {
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002,
> -	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002,
> +	SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
>   };
>   
>   #define sdma_v4_0_get_reg_offset(inst, offset) ( 0 == inst ? \
> @@ -115,18 +115,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
>   {
>   	switch (adev->asic_type) {
>   	case CHIP_VEGA10:
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_sdma_4,
>   						 ARRAY_SIZE(golden_settings_sdma_4));
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_sdma_vg10,
>   						 ARRAY_SIZE(golden_settings_sdma_vg10));
>   		break;
>   	case CHIP_RAVEN:
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_sdma_4_1,
>   						 ARRAY_SIZE(golden_settings_sdma_4_1));
> -		amdgpu_program_register_sequence(adev,
> +		soc15_program_register_sequence(adev,
>   						 golden_settings_sdma_rv1,
>   						 ARRAY_SIZE(golden_settings_sdma_rv1));
>   		break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7c88bcb..779c671 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -332,25 +332,34 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
>   	return true;
>   }
>   
> -static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
> -	{ SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)},
> -	{ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)},
> -	{ SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_STAT)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)},
> -	{ SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)},
> +struct soc15_allowed_register_entry {
> +	uint32_t hwip;
> +	uint32_t inst;
> +	uint32_t seg;
> +	uint32_t reg_offset;
> +	bool grbm_indexed;
> +};
> +
> +
> +static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
> +	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
> +	{ SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
> +	{ SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
> +	{ SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
>   };
>   
>   static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
> @@ -390,10 +399,13 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
>   			    u32 sh_num, u32 reg_offset, u32 *value)
>   {
>   	uint32_t i;
> +	struct soc15_allowed_register_entry  *en;
>   
>   	*value = 0;
>   	for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
> -		if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
> +		en = &soc15_allowed_read_registers[i];
> +		if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
> +					+ en->reg_offset))
>   			continue;
>   
>   		*value = soc15_get_register_value(adev,
> @@ -404,6 +416,47 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
>   	return -EINVAL;
>   }
>   
> +
> +/**
> + * soc15_program_register_sequence - program an array of registers.
> + *
> + * @adev: amdgpu_device pointer
> + * @regs: pointer to the register array
> + * @array_size: size of the register array
> + *
> + * Programs an array or registers with and and or masks.
> + * This is a helper for setting golden registers.
> + */
> +
> +void soc15_program_register_sequence(struct amdgpu_device *adev,
> +					     const u32 *regs,
> +					     const u32 array_size)
> +{
> +	u32 tmp, reg, and_mask, or_mask;
> +	int i;
> +
> +	if (array_size % 6)
> +		return;
> +
> +	for (i = 0; i < array_size; i +=6) {
> +		reg =  adev->reg_offset[regs[i + 0]][regs[i + 1]][regs[i + 2]] +
> +			regs[i + 3];
> +		and_mask = regs[i + 4];
> +		or_mask = regs[i + 5];
> +
> +		if (and_mask == 0xffffffff) {
> +			tmp = or_mask;
> +		} else {
> +			tmp = RREG32(reg);
> +			tmp &= ~and_mask;
> +			tmp |= or_mask;
> +		}
> +		WREG32(reg, tmp);
> +	}
> +
> +}
> +
> +
>   static int soc15_asic_reset(struct amdgpu_device *adev)
>   {
>   	u32 i;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index c34496f..4882307 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -33,6 +33,10 @@ void soc15_grbm_select(struct amdgpu_device *adev,
>   		    u32 me, u32 pipe, u32 queue, u32 vmid);
>   int soc15_set_ip_blocks(struct amdgpu_device *adev);
>   
> +void soc15_program_register_sequence(struct amdgpu_device *adev,
> +					     const u32 *registers,
> +					     const u32 array_size);
> +
>   int vega10_reg_base_init(struct amdgpu_device *adev);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index 62a6e21..7f73125 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -53,6 +53,9 @@ struct nbio_pcie_index_data {
>                                                           (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>                                                               (ip##_BASE__INST##inst##_SEG4 + reg)))))
>   
> +#define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg
> +
> +
>   #define WREG32_FIELD15(ip, idx, reg, field, val)	\
>   	WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
>   	(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg)	\
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 660fa41..6823c7b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1681,7 +1681,8 @@ static int uvd_v7_0_set_clockgating_state(void *handle,
>   static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
>   	.type = AMDGPU_RING_TYPE_UVD,
>   	.align_mask = 0xf,
> -	.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
> +	/*Fix me  if UVD_HWIP base or  mmUVD_NO_OP_BASE_IDX changed in future asic */
> +	.nop = PACKET0((0x7e00 + mmUVD_NO_OP), 0),
>   	.support_64bit_ptrs = false,
>   	.vmhub = AMDGPU_MMHUB,
>   	.get_rptr = uvd_v7_0_ring_get_rptr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index e4673f7..f93ca21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1100,7 +1100,7 @@ static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
>   static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
>   	.type = AMDGPU_RING_TYPE_VCN_DEC,
>   	.align_mask = 0xf,
> -	.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
> +	.nop = PACKET0(0x81ff, 0),
>   	.support_64bit_ptrs = false,
>   	.vmhub = AMDGPU_MMHUB,
>   	.get_rptr = vcn_v1_0_dec_ring_get_rptr,



More information about the amd-gfx mailing list