[PATCH] Revert "drm/amd/powerplay: Add support for CI asics to hwmgr"

Tom St Denis tom.stdenis at amd.com
Wed Oct 4 17:50:06 UTC 2017


On 04/10/17 01:39 PM, Deucher, Alexander wrote:
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
>> Of Tom St Denis
>> Sent: Wednesday, October 04, 2017 1:13 PM
>> To: amd-gfx at lists.freedesktop.org
>> Cc: StDenis, Tom
>> Subject: [PATCH] Revert "drm/amd/powerplay: Add support for CI asics to
>> hwmgr"
>>
>> The commit being reverted breaks Tonga support by causing visible
>> noise on the screen.  The original patch should have been
>> split up to begin with as adding CI functionality shouldn't
>> result in functional changes to non-CI platforms at the same time.
>>
>> This reverts commit 0b6b4cbf77c995a34a4ec3d705a636434dadc51a.
>>
>> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
>> ---
>>   drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c      |  58 +++++------
>>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 118 +++++-------
>> -----------
>>   2 files changed, 47 insertions(+), 129 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index 35e80c969737..089d55d4ad2c 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -53,7 +53,6 @@ static int hwmgr_set_user_specify_caps(struct
>> pp_hwmgr *hwmgr);
>>   static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
>>   static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
>>   static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
>> -static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
>>
>>   uint8_t convert_to_vid(uint16_t vddc)
>>   {
>> @@ -155,14 +154,6 @@ int hwmgr_early_init(struct pp_instance *handle)
>>   	hwmgr->reload_fw = 1;
>>
>>   	switch (hwmgr->chip_family) {
>> -	case AMDGPU_FAMILY_CI:
>> -		hwmgr->smumgr_funcs = &ci_smu_funcs;
>> -		ci_set_asic_special_caps(hwmgr);
>> -		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK
>> |
>> -					PP_ENABLE_GFX_CG_THRU_SMU);
>> -		hwmgr->pp_table_version = PP_TABLE_V0;
>> -		smu7_init_function_pointers(hwmgr);
>> -		break;
>>   	case AMDGPU_FAMILY_CZ:
>>   		hwmgr->smumgr_funcs = &cz_smu_funcs;
>>   		cz_init_function_pointers(hwmgr);
>> @@ -882,8 +873,28 @@ void phm_apply_dal_min_voltage_request(struct
>> pp_hwmgr *hwmgr)
>>
>>   void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
>>   {
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableVoltageTransition);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableEngineTransition);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableMemoryTransition);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableMGClockGating);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableMGCGTSSM);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableLSClockGating);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_Force3DClockSupport);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableLightSleep);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableMCLS);
>> +	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisablePowerGating);
>> +
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableDPM);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_DisableSMUUVDHandshake);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_ThermalAutoThrottling);
>> +
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_PCIEPerformanceRequest);
>>
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_NoOD5Support);
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_UserMaxClockForMultiDisplays);
>> +
>> +	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_VpuRecoveryInProgress);
>> +
>>   	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_UVDDPM);
>>   	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> PHM_PlatformCaps_VCEDPM);
>>
>> @@ -908,6 +919,7 @@ void hwmgr_init_default_caps(struct pp_hwmgr
>> *hwmgr)
>>
>>   	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> 	PHM_PlatformCaps_FanSpeedInTableIsRPM);
>> +
>>   	return;
>>   }
>>
>> @@ -956,8 +968,7 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr
>> *hwmgr, uint8_t voltage_type,
>>
>>   int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>>   {
>> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> -						PHM_PlatformCaps_EVV);
>> +
>>   	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> 	PHM_PlatformCaps_SQRamping);
>>   	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> @@ -983,8 +994,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>>
>>   int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>>   {
>> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> -						PHM_PlatformCaps_EVV);
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_SQRamping);
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> @@ -993,13 +1002,12 @@ int fiji_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>>   			PHM_PlatformCaps_TDRamping);
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_TCPRamping);
>> +
>>   	return 0;
>>   }
>>
>>   int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>>   {
>> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> -						PHM_PlatformCaps_EVV);
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_SQRamping);
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> @@ -1013,25 +1021,11 @@ int tonga_set_asic_special_caps(struct
>> pp_hwmgr *hwmgr)
>>   		      PHM_PlatformCaps_UVDPowerGating);
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   		      PHM_PlatformCaps_VCEPowerGating);
>> -	return 0;
>> -}
>>
>> -int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>> -{
>> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> -						PHM_PlatformCaps_EVV);
>> -	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> -			PHM_PlatformCaps_SQRamping);
>> -	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> -			PHM_PlatformCaps_DBRamping);
>> -	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> -			PHM_PlatformCaps_TDRamping);
>> -	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>> -			PHM_PlatformCaps_TCPRamping);
>>   	return 0;
>>   }
>>
>> -int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>> +int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>>   {
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_SQRamping);
>> @@ -1042,8 +1036,6 @@ int ci_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>>   	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_TCPRamping);
>>   	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> -
>> 	PHM_PlatformCaps_MemorySpreadSpectrumSupport);
>> -	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> -
>> 	PHM_PlatformCaps_EngineSpreadSpectrumSupport);
>> +		    PHM_PlatformCaps_EVV);
>>   	return 0;
>>   }
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 8dbe9148aad3..45ff94e4ec47 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -26,7 +26,6 @@
>>   #include <linux/module.h>
>>   #include <linux/slab.h>
>>   #include <asm/div64.h>
>> -#include <drm/amdgpu_drm.h>
>>   #include "pp_acpi.h"
>>   #include "ppatomctrl.h"
>>   #include "atombios.h"
>> @@ -585,20 +584,13 @@ static int smu7_setup_default_pcie_table(struct
>> pp_hwmgr *hwmgr)
>>   		data->dpm_table.pcie_speed_table.count = 6;
>>   	}
>>   	/* Populate last level for boot PCIE level, but do not increment count.
>> */
>> -	if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
>> -		for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
>> -			phm_setup_pcie_table_entry(&data-
>>> dpm_table.pcie_speed_table, i,
>> -				get_pcie_gen_support(data->pcie_gen_cap,
>> -						PP_Max_PCIEGen),
>> -				data-
>>> vbios_boot_state.pcie_lane_bootup_value);
>> -	} else {
>> -		phm_setup_pcie_table_entry(&data-
>>> dpm_table.pcie_speed_table,
>> +	phm_setup_pcie_table_entry(&data-
>>> dpm_table.pcie_speed_table,
>>   			data->dpm_table.pcie_speed_table.count,
>>   			get_pcie_gen_support(data->pcie_gen_cap,
>>   					PP_Min_PCIEGen),
>>   			get_pcie_lane_support(data->pcie_lane_cap,
>>   					PP_Max_PCIELane));
>> -	}
>> +
>>   	return 0;
>>   }
>>
>> @@ -674,7 +666,7 @@ static int smu7_setup_dpm_tables_v0(struct
>> pp_hwmgr *hwmgr)
>>   				allowed_vdd_sclk_table->entries[i].clk) {
>>   			data->dpm_table.sclk_table.dpm_levels[data-
>>> dpm_table.sclk_table.count].value =
>>   				allowed_vdd_sclk_table->entries[i].clk;
>> -			data->dpm_table.sclk_table.dpm_levels[data-
>>> dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
>> +			data->dpm_table.sclk_table.dpm_levels[data-
>>> dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
>>   			data->dpm_table.sclk_table.count++;
>>   		}
>>   	}
>> @@ -688,7 +680,7 @@ static int smu7_setup_dpm_tables_v0(struct
>> pp_hwmgr *hwmgr)
>>   			allowed_vdd_mclk_table->entries[i].clk) {
>>   			data->dpm_table.mclk_table.dpm_levels[data-
>>> dpm_table.mclk_table.count].value =
>>   				allowed_vdd_mclk_table->entries[i].clk;
>> -			data->dpm_table.mclk_table.dpm_levels[data-
>>> dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
>> +			data->dpm_table.mclk_table.dpm_levels[data-
>>> dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
>>   			data->dpm_table.mclk_table.count++;
>>   		}
>>   	}
>> @@ -948,24 +940,13 @@ static int smu7_enable_sclk_mclk_dpm(struct
>> pp_hwmgr *hwmgr)
>>
>>   		PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3,
>> CAC_EN, 0x1);
>>
>> -
>> -		if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, 0xc0400d30, 0x5);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
>> -			udelay(10);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
>> -		} else {
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
>> -			udelay(10);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
>> -			cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
>> -		}
>> +		cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
>> +		cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
>> +		cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
>> +		udelay(10);
>> +		cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
>> +		cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
>> +		cgs_write_ind_register(hwmgr->device,
>> CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
>>   	}
>>
>>   	return 0;
>> @@ -994,10 +975,6 @@ static int smu7_start_dpm(struct pp_hwmgr
>> *hwmgr)
>>   	PHM_WRITE_INDIRECT_FIELD(hwmgr->device,
>> CGS_IND_REG__PCIE,
>>   			SWRST_COMMAND_1, RESETLC, 0x0);
>>
>> -	if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
>> -		cgs_write_register(hwmgr->device, 0x1488,
>> -			(cgs_read_register(hwmgr->device, 0x1488) &
>> ~0x1));
>> -
>>   	if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
>>   		pr_err("Failed to enable Sclk DPM and Mclk DPM!");
>>   		return -EINVAL;
>> @@ -1389,29 +1366,12 @@ static void smu7_init_dpm_defaults(struct
>> pp_hwmgr *hwmgr)
>>   						&tmp3);
>>   		tmp3 = (tmp3 >> 5) & 0x3;
>>   		data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >>
>> 1)) & 0x3;
>> -	} else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
>> -		data->vddc_phase_shed_control = 1;
>> -	} else {
>> -		data->vddc_phase_shed_control = 0;
>> -	}
>> -
>> -	if (hwmgr->chip_id  == CHIP_HAWAII) {
>> -		data->thermal_temp_setting.temperature_low = 94500;
>> -		data->thermal_temp_setting.temperature_high = 95000;
>> -		data->thermal_temp_setting.temperature_shutdown =
>> 104000;
>> -	} else {
>> -		data->thermal_temp_setting.temperature_low = 99500;
>> -		data->thermal_temp_setting.temperature_high = 100000;
>> -		data->thermal_temp_setting.temperature_shutdown =
>> 104000;
>>   	}
>>
>>   	data->fast_watermark_threshold = 100;
>>   	if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
>>   			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
>>   		data->voltage_control =
>> SMU7_VOLTAGE_CONTROL_BY_SVID2;
>> -	else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
>> -			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
>> -		data->voltage_control =
>> SMU7_VOLTAGE_CONTROL_BY_GPIO;
>>
>>   	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_ControlVDDGFX)) {
>> @@ -1431,9 +1391,10 @@ static void smu7_init_dpm_defaults(struct
>> pp_hwmgr *hwmgr)
>>   			data->mvdd_control =
>> SMU7_VOLTAGE_CONTROL_BY_SVID2;
>>   	}
>>
>> -	if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
>> +	if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
>>   		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_ControlVDDGFX);
>> +	}
>>
>>   	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>>   			PHM_PlatformCaps_ControlVDDCI)) {
>> @@ -2290,7 +2251,7 @@ static int
>> smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
>>   		data->max_vddci_in_pptable =
>> (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table-
>>> count - 1].v;
>>   	}
>>
>> -	if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL &&
>> hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
>> +	if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL &&
>> hwmgr->dyn_state.vddci_dependency_on_mclk->count > 1)
>>   		hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
>> hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr-
>>> dyn_state.vddci_dependency_on_mclk->count - 1].v;
>>
>>   	return 0;
>> @@ -2306,38 +2267,10 @@ static int smu7_hwmgr_backend_fini(struct
>> pp_hwmgr *hwmgr)
>>   	return 0;
>>   }
>>
>> -static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
>> -{
>> -	uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
>> -	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr-
>>> backend);
>> -	int i;
>> -
>> -	if (atomctrl_get_leakage_id_from_efuse(hwmgr,
>> &efuse_voltage_id) == 0) {
>> -		for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
>> -			virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0
>> + i;
>> -			if
>> (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
>> -
>> 	virtual_voltage_id,
>> -
>> 	efuse_voltage_id) == 0) {
>> -				if (vddc != 0 && vddc != virtual_voltage_id) {
>> -					data-
>>> vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
>> -					data-
>>> vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
>> -					data->vddc_leakage.count++;
>> -				}
>> -				if (vddci != 0 && vddci != virtual_voltage_id) {
>> -					data-
>>> vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
>> -					data-
>>> vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
>> -					data->vddci_leakage.count++;
>> -				}
>> -			}
>> -		}
>> -	}
>> -	return 0;
>> -}
>> -
>>   static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
>>   {
>>   	struct smu7_hwmgr *data;
>> -	int result = 0;
>> +	int result;
>>
>>   	data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
>>   	if (data == NULL)
>> @@ -2348,15 +2281,11 @@ static int smu7_hwmgr_backend_init(struct
>> pp_hwmgr *hwmgr)
>>   	smu7_init_dpm_defaults(hwmgr);
>>
>>   	/* Get leakage voltage based on leakage ID. */
>> -	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>> -			PHM_PlatformCaps_EVV)) {
>> -		result = smu7_get_evv_voltages(hwmgr);
>> -		if (result) {
>> -			pr_info("Get EVV Voltage Failed.  Abort Driver
>> loading!\n");
>> -			return -EINVAL;
>> -		}
>> -	} else {
>> -		smu7_get_elb_voltages(hwmgr);
>> +	result = smu7_get_evv_voltages(hwmgr);
>> +
>> +	if (result) {
>> +		pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
>> +		return -EINVAL;
>>   	}
>>
>>   	if (hwmgr->pp_table_version == PP_TABLE_V1) {
>> @@ -3825,14 +3754,11 @@ static int
>> smu7_notify_link_speed_change_after_state_change(
>>   static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
>>   {
>>   	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr-
>>> backend);
>> -	int ret = 0;
>>
>> -	if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
>> +	if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK)
>>   		smum_send_msg_to_smc_with_parameter(hwmgr,
>>   			(PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data-
>>> frame_time_x2);
>> -		ret = (smum_send_msg_to_smc(hwmgr,
>> (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
>> -	}
>> -	return ret;
>> +	return (smum_send_msg_to_smc(hwmgr,
>> (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
>>   }
> 
> Does just reverting this last chunk fix the issue?  I think that is the issue.  Either way,  the patch is:
> Acked-by: Alex Deucher <alexander.deucher at amd.com>


Darn you... that's the only (non-CI) hunk I didn't revert ...

Reverting that fixes issues on Tonga.  I don't know if that opens issues 
on CI though.

Let's drop this patch (I just emailed the new one).

Tom


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