[PATCH] drm/amdgpu: correct reference clock value on vega10

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Ken.Wang at amd.com
> Sent: Wednesday, October 11, 2017 10:41 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Wang, Ken
> Subject: [PATCH] drm/amdgpu: correct reference clock value on vega10
> 
> From: Ken Wang <Ken.Wang at amd.com>
> 
> Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
> Signed-off-by: Ken Wang <Ken.Wang at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7839677..88d5498 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -279,10 +279,7 @@ static void soc15_init_golden_registers(struct
> amdgpu_device *adev)
>  }
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
> -	if (adev->asic_type == CHIP_VEGA10)
> -		return adev->clock.spll.reference_freq/4;
> -	else
> -		return adev->clock.spll.reference_freq;
> +	return adev->clock.spll.reference_freq;
>  }
> 
> 
> --
> 2.7.4
> 
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