[PATCH v3] drm/amd/powerplay: Remove unnecessary cast on void pointer
kbuild test robot
lkp at intel.com
Mon Oct 16 21:17:50 UTC 2017
Hi Harsha,
[auto build test WARNING on v4.14-rc3]
[cannot apply to drm/drm-next next-20171013]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Harsha-Sharma/drm-amd-powerplay-Remove-unnecessary-cast-on-void-pointer/20171017-001535
config: x86_64-randconfig-a0-10170343 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8) 4.4.7
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c: In function 'smu7_get_pp_table_entry_callback_func_v1':
>> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:2954: warning: initialization from incompatible pointer type
vim +2954 drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c
2948
2949 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
2950 void *state, struct pp_power_state *power_state,
2951 void *pp_table, uint32_t classification_flag)
2952 {
2953 struct smu7_hwmgr *data = hwmgr->backend;
> 2954 struct smu7_power_state *smu7_power_state = &(power_state->hardware);
2955 struct smu7_performance_level *performance_level;
2956 ATOM_Tonga_State *state_entry = state;
2957 ATOM_Tonga_POWERPLAYTABLE *powerplay_table = pp_table;
2958 PPTable_Generic_SubTable_Header *sclk_dep_table =
2959 (PPTable_Generic_SubTable_Header *)
2960 (((unsigned long)powerplay_table) +
2961 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
2962
2963 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
2964 (ATOM_Tonga_MCLK_Dependency_Table *)
2965 (((unsigned long)powerplay_table) +
2966 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
2967
2968 /* The following fields are not initialized here: id orderedList allStatesList */
2969 power_state->classification.ui_label =
2970 (le16_to_cpu(state_entry->usClassification) &
2971 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
2972 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
2973 power_state->classification.flags = classification_flag;
2974 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
2975
2976 power_state->classification.temporary_state = false;
2977 power_state->classification.to_be_deleted = false;
2978
2979 power_state->validation.disallowOnDC =
2980 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
2981 ATOM_Tonga_DISALLOW_ON_DC));
2982
2983 power_state->pcie.lanes = 0;
2984
2985 power_state->display.disableFrameModulation = false;
2986 power_state->display.limitRefreshrate = false;
2987 power_state->display.enableVariBright =
2988 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
2989 ATOM_Tonga_ENABLE_VARIBRIGHT));
2990
2991 power_state->validation.supportedPowerLevels = 0;
2992 power_state->uvd_clocks.VCLK = 0;
2993 power_state->uvd_clocks.DCLK = 0;
2994 power_state->temperatures.min = 0;
2995 power_state->temperatures.max = 0;
2996
2997 performance_level = &(smu7_power_state->performance_levels
2998 [smu7_power_state->performance_level_count++]);
2999
3000 PP_ASSERT_WITH_CODE(
3001 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
3002 "Performance levels exceeds SMC limit!",
3003 return -EINVAL);
3004
3005 PP_ASSERT_WITH_CODE(
3006 (smu7_power_state->performance_level_count <=
3007 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3008 "Performance levels exceeds Driver limit!",
3009 return -EINVAL);
3010
3011 /* Performance levels are arranged from low to high. */
3012 performance_level->memory_clock = mclk_dep_table->entries
3013 [state_entry->ucMemoryClockIndexLow].ulMclk;
3014 if (sclk_dep_table->ucRevId == 0)
3015 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3016 [state_entry->ucEngineClockIndexLow].ulSclk;
3017 else if (sclk_dep_table->ucRevId == 1)
3018 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3019 [state_entry->ucEngineClockIndexLow].ulSclk;
3020 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3021 state_entry->ucPCIEGenLow);
3022 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3023 state_entry->ucPCIELaneHigh);
3024
3025 performance_level = &(smu7_power_state->performance_levels
3026 [smu7_power_state->performance_level_count++]);
3027 performance_level->memory_clock = mclk_dep_table->entries
3028 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3029
3030 if (sclk_dep_table->ucRevId == 0)
3031 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3032 [state_entry->ucEngineClockIndexHigh].ulSclk;
3033 else if (sclk_dep_table->ucRevId == 1)
3034 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3035 [state_entry->ucEngineClockIndexHigh].ulSclk;
3036
3037 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3038 state_entry->ucPCIEGenHigh);
3039 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3040 state_entry->ucPCIELaneHigh);
3041
3042 return 0;
3043 }
3044
---
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