[PATCH 2/3] drm/amdgpu: report more amdgpu_fence_info v2

[Liu, Monk]

Okay leave it, we may need OS preemption in future so it still can be used for that purpose

Reviewed-by: Monk Liu <monk.liu at amd.com>


-----Original Message-----
From: Ding, Pixel 
Sent: 2017年10月17日 15:56
To: Liu, Monk <Monk.Liu at amd.com>; amd-gfx at lists.freedesktop.org; Koenig, Christian <Christian.Koenig at amd.com>
Cc: Li, Bingley <Bingley.Li at amd.com>; Sun, Gary <Gary.Sun at amd.com>
Subject: Re: [PATCH 2/3] drm/amdgpu: report more amdgpu_fence_info v2

Why? The fence WB is always 8 DW.
— 
Sincerely Yours,
Pixel







On 17/10/2017, 3:49 PM, "Liu, Monk" <Monk.Liu at amd.com> wrote:

>Please use if (amdgpu_sriov_vf())
>To protect your added part
>
>-----Original Message-----
>From: Pixel Ding [mailto:Pixel.Ding at amd.com] 
>Sent: 2017年10月17日 14:38
>To: amd-gfx at lists.freedesktop.org; Liu, Monk <Monk.Liu at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>
>Cc: Li, Bingley <Bingley.Li at amd.com>; Sun, Gary <Gary.Sun at amd.com>; Ding, Pixel <Pixel.Ding at amd.com>
>Subject: [PATCH 2/3] drm/amdgpu: report more amdgpu_fence_info v2
>
>From: pding <Pixel.Ding at amd.com>
>
>Only for GFX ring. This can help checking MCBP feature.
>
>v2: report more fence offs.
>
>The fence at the end of the frame will indicate the completion status.
>If the frame completed normally, the fence is written to the address given in the EVENT_WRITE_EOP packet. If preemption occurred in the previous IB the address is adjusted by 2 DWs. If work submitted in the frame was reset before completion, the fence address is adjusted by four DWs. In the case that preemption occurred, and before preemption completed a reset was initiated, the address will be adjusted with six DWs
>
>Signed-off-by: pding <Pixel.Ding at amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
>index 09d5a5c..688740e 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
>@@ -645,6 +645,19 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
> 			   atomic_read(&ring->fence_drv.last_seq));
> 		seq_printf(m, "Last emitted        0x%08x\n",
> 			   ring->fence_drv.sync_seq);
>+
>+		if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
>+			continue;
>+
>+		/* set in CP_VMID_PREEMPT and preemption occurred */
>+		seq_printf(m, "Last preempted      0x%08x\n",
>+			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
>+		/* set in CP_VMID_RESET and reset occurred */
>+		seq_printf(m, "Last reset          0x%08x\n",
>+			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
>+		/* Both preemption and reset occurred */
>+		seq_printf(m, "Last both           0x%08x\n",
>+			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
> 	}
> 	return 0;
> }
>--
>2.9.5
>