[PATCH] drm/amdgpu: always consider virualised device for checking post (v3)

Deucher, Alexander Alexander.Deucher at amd.com
Thu Oct 19 14:03:51 UTC 2017


> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Pixel Ding
> Sent: Thursday, October 19, 2017 1:43 AM
> To: amd-gfx at lists.freedesktop.org; Deucher, Alexander
> Cc: Sun, Gary; Ding, Pixel
> Subject: [PATCH] drm/amdgpu: always consider virualised device for
> checking post (v3)
> 
> From: pding <Pixel.Ding at amd.com>
> 
> v2:
>  - only change in IGP reading bios.
> v3:
>  - merge functions and apply on all bios checking.
> 
> Signed-off-by: pding <Pixel.Ding at amd.com>

Please add a better patch description.  E.g.,

Merge the vpost functions to avoid confusion and take
virtualization into account in all cases.

With that updated, the patch is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 41 +++++++++++++-----
> ------------
>  1 file changed, 18 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a01caba..9de5a00 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -745,27 +745,6 @@ bool amdgpu_need_post(struct amdgpu_device
> *adev)
>  {
>  	uint32_t reg;
> 
> -	if (adev->has_hw_reset) {
> -		adev->has_hw_reset = false;
> -		return true;
> -	}
> -
> -	/* bios scratch used on CIK+ */
> -	if (adev->asic_type >= CHIP_BONAIRE)
> -		return amdgpu_atombios_scratch_need_asic_init(adev);
> -
> -	/* check MEM_SIZE for older asics */
> -	reg = amdgpu_asic_get_config_memsize(adev);
> -
> -	if ((reg != 0) && (reg != 0xffffffff))
> -		return false;
> -
> -	return true;
> -
> -}
> -
> -static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
> -{
>  	if (amdgpu_sriov_vf(adev))
>  		return false;
> 
> @@ -788,7 +767,23 @@ static bool amdgpu_vpost_needed(struct
> amdgpu_device *adev)
>  				return true;
>  		}
>  	}
> -	return amdgpu_need_post(adev);
> +
> +	if (adev->has_hw_reset) {
> +		adev->has_hw_reset = false;
> +		return true;
> +	}
> +
> +	/* bios scratch used on CIK+ */
> +	if (adev->asic_type >= CHIP_BONAIRE)
> +		return amdgpu_atombios_scratch_need_asic_init(adev);
> +
> +	/* check MEM_SIZE for older asics */
> +	reg = amdgpu_asic_get_config_memsize(adev);
> +
> +	if ((reg != 0) && (reg != 0xffffffff))
> +		return false;
> +
> +	return true;
>  }
> 
>  /**
> @@ -2252,7 +2247,7 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
>  	amdgpu_device_detect_sriov_bios(adev);
> 
>  	/* Post card if necessary */
> -	if (amdgpu_vpost_needed(adev)) {
> +	if (amdgpu_need_post(adev)) {
>  		if (!adev->bios) {
>  			dev_err(adev->dev, "no vBIOS found\n");
>  			amdgpu_vf_error_put(adev,
> AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
> --
> 2.9.5
> 
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