[PATCH 6/8] drm/amd/display: enable GPU VM support

Christian König christian.koenig at amd.com
Fri Oct 27 15:01:56 UTC 2017

Am 27.10.2017 um 16:58 schrieb Michel Dänzer:
> On 27/10/17 04:48 PM, Christian König wrote:
>> Am 27.10.2017 um 16:37 schrieb Harry Wentland:
>>> On 2017-10-26 12:06 PM, Christian König wrote:
>>>> From: Christian König <christian.koenig at amd.com>
>>>> Just set the bit so that DC does the hardware programming.
>>>> Signed-off-by: Christian König <christian.koenig at amd.com>
>>>> ---
>>>>    drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
>>>>    1 file changed, 2 insertions(+)
>>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> index 2188f20..ed4351a 100644
>>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> @@ -417,6 +417,8 @@ static int amdgpu_dm_init(struct amdgpu_device
>>>> *adev)
>>>>          init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
>>>>    +    init_data.flags.gpu_vm_support = true;
>>>> +
>>> Hi Christian,
>>> what ASIC has this been tested on?
>> Carizzo.
>>> I'm not sure that this won't break dGPU. dGPU doesn't have vm_support
>>> but I think DC will still try to write the same registers as for CZ on
>>> dGPU if we enable this. We at least need to make sure it doesn't blow up.
>> Yeah, as Tom already stumbled over as well it causes a warning on Tonga.
>> Currently giving it a spin on Polaris.
>>> As for Raven we use this flag on Windows but only tested the case
>>> where VM is actually programmed. If VM isn't programmed it might still
>>> work but we'd need to give that a spin.
>> Without this flag tilling fails and only displays a quite unusual pattern.
>> I would actually prefer if we can completely remove this flag and
>> instead always enable the VM programming on supported hardware.
>> Is there any downside on doing so?
> Is there a particular use-case for scanout from system memory with a
> dGPU? Otherwise I suspect it's better not to bother, because the failure
> mode might be pretty bad if the PCIe link can't keep up with scanout.

That's true and I actually didn't want to suggest that we scanout from 
system memory on dGPUs.

But setting up the tilling information in the DCE/DCN VM block anyway 
looks harmless to me.

And scanning out from scattered VRAM at some point still seems to make 
sense to me.


More information about the amd-gfx mailing list