unclear code in vega10 pp

[Zhu, Rex]

Yes.

Best Regards
Rex

-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of Tom St Denis
Sent: Wednesday, September 06, 2017 12:23 AM
To: amd-gfx at lists.freedesktop.org
Subject: Re: unclear code in vega10 pp

After seeing this style a few other places in the same file are they just padding out the rest of the array with the highest setting?

Tom

On 05/09/17 12:18 PM, Tom St Denis wrote:
> In vega10_populate_smc_link_levels(): there's this bit
> 
>      j = i - 1;
>      while (i < NUM_LINK_LEVELS) {
>          pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
>          pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
> 
>          result = vega10_populate_single_lclk_level(hwmgr,
>                  pcie_table->lclk[j], &(pp_table->LclkDid[i]));
>          if (result) {
>              pr_info("Populate LClock Level %d Failed!\n", i);
>              return result;
>          }
>          i++;
>      }
> 
> It seems 'j' isn't changing so it's spamming multiple entries in the 
> lclkdid[] array based on the same entries from the pcie_table->pcie*[j].
> 
> Is that intentional or is a ++ or -- to j missing?
> 
> Cheers,
> Tom
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> amd-gfx at lists.freedesktop.org
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