[PATCH 2/6] Reorganize, rename, move and split some VCE 1 defines.
Deucher, Alexander
Alexander.Deucher at amd.com
Mon Sep 11 16:06:37 UTC 2017
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Alexandre Demers
> Sent: Thursday, September 07, 2017 10:49 PM
> To: amd-gfx at lists.freedesktop.org
> Subject: [PATCH 2/6] Reorganize, rename, move and split some VCE 1
> defines.
>
> For consistency with other files under amdgpu driver.
>
> Signed-off-by: Alexandre Demers <alexandre.f.demers at gmail.com>
> ---
> drivers/gpu/drm/amd/amdgpu/si.c | 15 +++-
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 5 +-
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 21 +++---
> drivers/gpu/drm/amd/amdgpu/sid.h | 70 -------------------
> .../gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h | 80
> +++++++++++++---------
> .../drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h | 13 +++-
> 6 files changed, 89 insertions(+), 115 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c
> b/drivers/gpu/drm/amd/amdgpu/si.c
> index c0b1aabf282f..08998639daeb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -38,15 +38,26 @@
> #include "gmc_v6_0.h"
> #include "si_dma.h"
> #include "dce_v6_0.h"
> +#include "vce_v1_0.h"
> #include "si.h"
> #include "dce_virtual.h"
> +
> #include "gca/gfx_6_0_d.h"
> -#include "oss/oss_1_0_d.h"
> +
> #include "gmc/gmc_6_0_d.h"
> +
> #include "dce/dce_6_0_d.h"
> -#include "uvd/uvd_4_0_d.h"
> +
> #include "bif/bif_3_0_d.h"
>
> +#include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
> +
> +#include "uvd/uvd_4_0_d.h"
> +
> +#include "smu/smu_7_0_1_d.h"
> +#include "smu/smu_7_0_1_sh_mask.h"
> +
I'm not sure I understand the point of the changes to this file.
> static const u32 tahiti_golden_registers[] =
> {
> mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 112969f3301a..fd50ab9933c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -26,6 +26,9 @@
> #include "amdgpu_trace.h"
> #include "sid.h"
>
> +#include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
> +
> const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
> {
> DMA0_REGISTER_OFFSET,
> @@ -587,7 +590,7 @@ static int si_dma_resume(void *handle)
> static bool si_dma_is_idle(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> - u32 tmp = RREG32(SRBM_STATUS2);
> + u32 tmp = RREG32(mmSRBM_STATUS2);
>
> if (tmp & (DMA_BUSY_MASK | DMA1_BUSY_MASK))
> return false;
This should be a separate patch.
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index e66084211c74..8fb9d00beea8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -26,6 +26,9 @@
> #include "sid.h"
> #include "si_ih.h"
>
> +#include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
> +
> static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
>
> static void si_ih_enable_interrupts(struct amdgpu_device *adev)
> @@ -39,7 +42,7 @@ static void si_ih_enable_interrupts(struct
> amdgpu_device *adev)
> WREG32(IH_RB_CNTL, ih_rb_cntl);
> adev->irq.ih.enabled = true;
> }
> -
> +
> static void si_ih_disable_interrupts(struct amdgpu_device *adev)
> {
> u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
> @@ -207,7 +210,7 @@ static int si_ih_resume(void *handle)
> static bool si_ih_is_idle(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> - u32 tmp = RREG32(SRBM_STATUS);
> + u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> return false;
> @@ -233,23 +236,23 @@ static int si_ih_soft_reset(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> u32 srbm_soft_reset = 0;
> - u32 tmp = RREG32(SRBM_STATUS);
> + u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> srbm_soft_reset |=
> SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
>
> if (srbm_soft_reset) {
> - tmp = RREG32(SRBM_SOFT_RESET);
> + tmp = RREG32(mmSRBM_SOFT_RESET);
> tmp |= srbm_soft_reset;
> - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
> - WREG32(SRBM_SOFT_RESET, tmp);
> - tmp = RREG32(SRBM_SOFT_RESET);
> + dev_info(adev->dev, "mmSRBM_SOFT_RESET=0x%08X\n",
> tmp);
> + WREG32(mmSRBM_SOFT_RESET, tmp);
> + tmp = RREG32(mmSRBM_SOFT_RESET);
>
> udelay(50);
>
> tmp &= ~srbm_soft_reset;
> - WREG32(SRBM_SOFT_RESET, tmp);
> - tmp = RREG32(SRBM_SOFT_RESET);
> + WREG32(mmSRBM_SOFT_RESET, tmp);
> + tmp = RREG32(mmSRBM_SOFT_RESET);
>
> udelay(50);
> }
Same here.
> diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h
> b/drivers/gpu/drm/amd/amdgpu/sid.h
> index c57eff159374..279d183f06c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sid.h
> +++ b/drivers/gpu/drm/amd/amdgpu/sid.h
> @@ -331,7 +331,6 @@
> # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
> # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
>
> -#define SRBM_STATUS 0x394
> #define GRBM_RQ_PENDING (1 << 5)
> #define VMC_BUSY (1 << 8)
> #define MCB_BUSY (1 << 9)
> @@ -341,7 +340,6 @@
> #define SEM_BUSY (1 << 14)
> #define IH_BUSY (1 << 17)
>
> -#define SRBM_SOFT_RESET 0x398
> #define SOFT_RESET_BIF (1 <<
> 1)
> #define SOFT_RESET_DC (1 <<
> 5)
> #define SOFT_RESET_DMA1 (1 <<
> 6)
> @@ -364,7 +362,6 @@
> #define SRBM_INT_CNTL 0x3A8
> #define SRBM_INT_ACK 0x3AA
>
> -#define SRBM_STATUS2 0x3B1
> #define DMA_BUSY (1 << 5)
> #define DMA1_BUSY (1 << 6)
>
> @@ -1941,54 +1938,6 @@
> #define DMA_PACKET_POLL_REG_MEM
> 0xe
> #define DMA_PACKET_NOP 0xf
>
> -#define VCE_STATUS 0x20004
> -#define VCE_VCPU_CNTL 0x20014
> -#define VCE_CLK_EN (1 << 0)
> -#define VCE_VCPU_CACHE_OFFSET0 0x20024
> -#define VCE_VCPU_CACHE_SIZE0 0x20028
> -#define VCE_VCPU_CACHE_OFFSET1 0x2002c
> -#define VCE_VCPU_CACHE_SIZE1 0x20030
> -#define VCE_VCPU_CACHE_OFFSET2 0x20034
> -#define VCE_VCPU_CACHE_SIZE2 0x20038
> -#define VCE_SOFT_RESET 0x20120
> -#define VCE_ECPU_SOFT_RESET (1 << 0)
> -#define VCE_FME_SOFT_RESET (1 << 2)
> -#define VCE_RB_BASE_LO2 0x2016c
> -#define VCE_RB_BASE_HI2 0x20170
> -#define VCE_RB_SIZE2 0x20174
> -#define VCE_RB_RPTR2 0x20178
> -#define VCE_RB_WPTR2 0x2017c
> -#define VCE_RB_BASE_LO 0x20180
> -#define VCE_RB_BASE_HI 0x20184
> -#define VCE_RB_SIZE 0x20188
> -#define VCE_RB_RPTR 0x2018c
> -#define VCE_RB_WPTR 0x20190
> -#define VCE_CLOCK_GATING_A 0x202f8
> -#define VCE_CLOCK_GATING_B 0x202fc
> -#define VCE_UENC_CLOCK_GATING 0x205bc
> -#define VCE_UENC_REG_CLOCK_GATING 0x205c0
> -#define VCE_FW_REG_STATUS 0x20e10
> -# define VCE_FW_REG_STATUS_BUSY (1 << 0)
> -# define VCE_FW_REG_STATUS_PASS (1 << 3)
> -# define VCE_FW_REG_STATUS_DONE (1 << 11)
> -#define VCE_LMI_FW_START_KEYSEL 0x20e18
> -#define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
> -#define VCE_LMI_CTRL2 0x20e74
> -#define VCE_LMI_CTRL 0x20e98
> -#define VCE_LMI_VM_CTRL 0x20ea0
> -#define VCE_LMI_SWAP_CNTL 0x20eb4
> -#define VCE_LMI_SWAP_CNTL1 0x20eb8
> -#define VCE_LMI_CACHE_CTRL 0x20ef4
> -
> -#define VCE_CMD_NO_OP 0x00000000
> -#define VCE_CMD_END 0x00000001
> -#define VCE_CMD_IB 0x00000002
> -#define VCE_CMD_FENCE 0x00000003
> -#define VCE_CMD_TRAP 0x00000004
> -#define VCE_CMD_IB_AUTO 0x00000005
> -#define VCE_CMD_SEMAPHORE 0x00000006
> -
> -
> //#dce stupp
> /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
> #define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/4
> @@ -2320,11 +2269,6 @@
> # define NI_INPUT_GAMMA_XVYCC_222 3
> # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
>
> -#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
> -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
> -#define SRBM_STATUS__IH_BUSY_MASK 0x20000
> -#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
> -
> #define BLACKOUT_MODE_MASK 0x00000007
> #define VGA_RENDER_CONTROL 0xC0
> #define R_000300_VGA_RENDER_CONTROL 0xC0
> @@ -2411,18 +2355,6 @@
> #define MC_SEQ_MISC0__MT__HBM 0x60000000
> #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
>
> -#define SRBM_STATUS__MCB_BUSY_MASK 0x200
> -#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
> -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
> -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
> -#define SRBM_STATUS__MCC_BUSY_MASK 0x800
> -#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
> -#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
> -#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
> -#define SRBM_STATUS__VMC_BUSY_MASK 0x100
> -#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
> -
> -
> #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
> #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK
> 0x4000000
> #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
> @@ -2447,8 +2379,6 @@
>
> #define PCIE_BUS_CLK 10000
> #define TCLK (PCIE_BUS_CLK / 10)
> -#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
> -#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
> #define PCIE_PORT_INDEX 0xe
> #define PCIE_PORT_DATA 0xf
> #define EVERGREEN_PIF_PHY0_INDEX 0x8
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
> b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
> index 2176548e9203..2e4841a08742 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
> @@ -23,42 +23,58 @@
> #ifndef VCE_1_0_D_H
> #define VCE_1_0_D_H
>
> -#define mmVCE_CLOCK_GATING_A 0x80BE
> -#define mmVCE_CLOCK_GATING_B 0x80BF
> -#define mmVCE_LMI_CACHE_CTRL 0x83BD
> -#define mmVCE_LMI_CTRL 0x83A6
> -#define mmVCE_LMI_CTRL2 0x839D
> -#define mmVCE_LMI_MISC_CTRL 0x83B5
> -#define mmVCE_LMI_STATUS 0x83A7
> -#define mmVCE_LMI_SWAP_CNTL 0x83AD
> -#define mmVCE_LMI_SWAP_CNTL1 0x83AE
> -#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397
> -#define mmVCE_LMI_VM_CTRL 0x83A8
> -#define mmVCE_RB_ARB_CTRL 0x809F
> -#define mmVCE_RB_BASE_HI 0x8061
> -#define mmVCE_RB_BASE_HI2 0x805C
> -#define mmVCE_RB_BASE_LO 0x8060
> +/* Imported from sid.h or cleaned up */
> +// #define VCE_FW_REG_STATUS 0x20e10
> +// #define VCE_LMI_FW_START_KEYSEL
> 0x20e18
> +// #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
> +
> +#define VCE_CMD_NO_OP 0x00000000
> +#define VCE_CMD_END 0x00000001
> +#define VCE_CMD_IB 0x00000002
> +#define VCE_CMD_FENCE 0x00000003
> +#define VCE_CMD_TRAP 0x00000004
> +#define VCE_CMD_IB_AUTO 0x00000005
> +#define VCE_CMD_SEMAPHORE 0x00000006
> +
Please keep the vce commands in sid.h for consistency.
> +
> +
> +#define mmVCE_STATUS 0x8001
> +#define mmVCE_VCPU_CNTL 0x8005
> +#define mmVCE_VCPU_CACHE_OFFSET0 0x8009
> +#define mmVCE_VCPU_CACHE_SIZE0 0x800A
> +#define mmVCE_VCPU_CACHE_OFFSET1 0x800B
> +#define mmVCE_VCPU_CACHE_SIZE1 0x800C
> +#define mmVCE_VCPU_CACHE_OFFSET2 0x800D
> +#define mmVCE_VCPU_CACHE_SIZE2 0x800E
> +#define mmVCE_SOFT_RESET 0x8048
> #define mmVCE_RB_BASE_LO2 0x805B
> -#define mmVCE_RB_RPTR 0x8063
> +#define mmVCE_RB_BASE_HI2 0x805C
> +#define mmVCE_RB_SIZE2 0x805D
> #define mmVCE_RB_RPTR2 0x805E
> +#define mmVCE_RB_WPTR2 0x805F
> +#define mmVCE_RB_BASE_LO 0x8060
> +#define mmVCE_RB_BASE_HI 0x8061
> #define mmVCE_RB_SIZE 0x8062
> -#define mmVCE_RB_SIZE2 0x805D
> +#define mmVCE_RB_RPTR 0x8063
> #define mmVCE_RB_WPTR 0x8064
> -#define mmVCE_RB_WPTR2 0x805F
> -#define mmVCE_SOFT_RESET 0x8048
> -#define mmVCE_STATUS 0x8001
> -#define mmVCE_SYS_INT_ACK 0x8341
> -#define mmVCE_SYS_INT_EN 0x8340
> -#define mmVCE_SYS_INT_STATUS 0x8341
> -#define mmVCE_UENC_CLOCK_GATING 0x816F
> +#define mmVCE_RB_ARB_CTRL 0x809F
> +#define mmVCE_CLOCK_GATING_A 0x80BE
> +#define mmVCE_CLOCK_GATING_B 0x80BF
> #define mmVCE_UENC_DMA_DCLK_CTRL 0x8250
> +#define mmVCE_CGTT_CLK_OVERRIDE 0x81e8
> +#define mmVCE_UENC_CLOCK_GATING 0x816F
> #define mmVCE_UENC_REG_CLOCK_GATING 0x8170
> -#define mmVCE_VCPU_CACHE_OFFSET0 0x8009
> -#define mmVCE_VCPU_CACHE_OFFSET1 0x800B
> -#define mmVCE_VCPU_CACHE_OFFSET2 0x800D
> -#define mmVCE_VCPU_CACHE_SIZE0 0x800A
> -#define mmVCE_VCPU_CACHE_SIZE1 0x800C
> -#define mmVCE_VCPU_CACHE_SIZE2 0x800E
> -#define mmVCE_VCPU_CNTL 0x8005
> +#define mmVCE_SYS_INT_EN 0x8340
> +#define mmVCE_SYS_INT_STATUS 0x8341
> +#define mmVCE_SYS_INT_ACK 0x8341
> +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397
> +#define mmVCE_LMI_CTRL2 0x839D
> +#define mmVCE_LMI_CTRL 0x83A6
> +#define mmVCE_LMI_STATUS 0x83A7
> +#define mmVCE_LMI_VM_CTRL 0x83A8
> +#define mmVCE_LMI_SWAP_CNTL 0x83AD
> +#define mmVCE_LMI_SWAP_CNTL1 0x83AE
> +#define mmVCE_LMI_MISC_CTRL 0x83B5
> +#define mmVCE_LMI_CACHE_CTRL 0x83BD
>
> -#endif
> +#endif /* VCE_1_0_D_H */
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
> b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
> index ea5b26b11cb1..0653a4e1d59f 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
> @@ -23,6 +23,17 @@
> #ifndef VCE_1_0_SH_MASK_H
> #define VCE_1_0_SH_MASK_H
>
> +/* Imported from sid.h or cleaned up */
> +#define VCE_CLK_EN (1 << 0)
> +#define VCE_ECPU_SOFT_RESET (1 << 0)
> +#define VCE_FME_SOFT_RESET (1 << 2)
> +#define CGC_DYN_CLOCK_MODE (1 << 16)
> +#define VCE_FW_REG_STATUS_BUSY (1 << 0)
> +#define VCE_FW_REG_STATUS_PASS (1 << 3)
> +#define VCE_FW_REG_STATUS_DONE (1 << 11)
> +
Please use proper formating for these to match the other bitfield definitions in the file. E.g., __MASK and __SHIFT.
> +
> +
> #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L
> #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000
> #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
> @@ -96,4 +107,4 @@
> #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
> #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012
>
> -#endif
> +#endif /* VCE_1_0_SH_MASK_H */
> --
> 2.14.1
>
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