[PATCH] drm/amdgpu/vce4: remove interrupt mask clearance for SRIOV

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Xiangliang.Yu
> Sent: Thursday, September 14, 2017 3:59 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Yu, Xiangliang; Liu, Leo
> Subject: [PATCH] drm/amdgpu/vce4: remove interrupt mask clearance for
> SRIOV
> 
> For SRIOV, the clearance has been moved to firmware. So don't need
> it any more.
> 

It would be good to check if we need this on bare metal as well.  I'd like to try and keep as much code common as possible.

> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 11134d5..d5dc6ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -1011,9 +1011,10 @@ static int vce_v4_0_process_interrupt(struct
> amdgpu_device *adev,
>  {
>  	DRM_DEBUG("IH: VCE\n");
> 
> -	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_STATUS),
> -
> 	VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MAS
> K,
> -
> 	~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MA
> SK);
> +	if (!amdgpu_sriov_vf(adev))
> +		WREG32_P(SOC15_REG_OFFSET(VCE, 0,
> mmVCE_SYS_INT_STATUS),
> +
> VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK,
> +
> ~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK);
> 
>  	switch (entry->src_data[0]) {
>  	case 0:
> --
> 2.7.4
> 
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