[PATCH 1/2] drm/amdgpu: New header for fields needed to determine state of ECC.

[David Panariti]

Add header file with ECC field definitions (MASKs and SHIFTs).

Change-Id: I6e420f11db8e701402088a5bc47f641d5ac41c47
Signed-off-by: David Panariti <David.Panariti at amd.com>
---
 .../include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h  | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
new file mode 100644
index 0000000..1ec5633
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_SH_MASK_HEADER
+#define _umc_6_0_SH_MASK_HEADER
+
+#define UMCCH0_0_EccCtrl__RdEccEn_MASK   0x00000400L
+#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT   0xa
+#define UMCCH0_0_EccCtrl__WrEccEn_MASK   0x00000001L
+#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT   0x0
+#define UMCCH0_0_UMC_CONFIG__DramReady_MASK   0x80000000L
+#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT   0x1f
+#define UMCCH0_0_UmcLocalCap__EccDis_MASK   0x00000001L
+#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT   0x0
+
+#endif
-- 
2.7.4