[PATCH] drm/amdgpu: Set the correct value for PDEs/PTEs of ATC memory

[Alex Deucher]

On Tue, Sep 26, 2017 at 7:30 PM, Yong Zhao <yong.zhao at amd.com> wrote:
> From: Yong Zhao <Yong.Zhao at amd.com>
>
> Without the additional bits set in PDEs/PTEs, the ATC memory access
> would have failed.
>
> Change-Id: I28429ef6d39cdb01dc6f17fea4264ee22d7121d4
> Signed-off-by: Yong Zhao <yong.zhao at amd.com>

Glad we finally got this sorted.
Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 8fcc743..c848b7c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -33,6 +33,8 @@
>  #include "amdgpu.h"
>  #include "amdgpu_trace.h"
>
> +#include "vega10/vega10_enum.h"
> +
>  /*
>   * PASID manager
>   *
> @@ -108,6 +110,13 @@ INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
>  #undef START
>  #undef LAST
>
> +#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM      \
> +                               | AMDGPU_PTE_SNOOPED    \
> +                               | AMDGPU_PTE_EXECUTABLE \
> +                               | AMDGPU_PTE_READABLE   \
> +                               | AMDGPU_PTE_WRITEABLE  \
> +                               | AMDGPU_PTE_MTYPE(MTYPE_CC))
> +
>  /* Local structure. Encapsulate some VM table update parameters to reduce
>   * the number of function parameters
>   */
> @@ -328,9 +337,10 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>                                 AMDGPU_GEM_CREATE_SHADOW);
>
>         if (vm->pte_support_ats) {
> -               init_value = AMDGPU_PTE_SYSTEM;
> +               init_value = AMDGPU_PTE_DEFAULT_ATC;
>                 if (level != adev->vm_manager.num_level - 1)
>                         init_value |= AMDGPU_PDE_PTE;
> +
>         }
>
>         /* walk over the address space and allocate the page tables */
> @@ -2017,7 +2027,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
>                 list_del(&mapping->list);
>
>                 if (vm->pte_support_ats)
> -                       init_pte_value = AMDGPU_PTE_SYSTEM;
> +                       init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
>
>                 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
>                                                 mapping->start, mapping->last,
> @@ -2627,7 +2637,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>
>                 if (adev->asic_type == CHIP_RAVEN) {
>                         vm->pte_support_ats = true;
> -                       init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE;
> +                       init_pde_value = AMDGPU_PTE_DEFAULT_ATC
> +                                       | AMDGPU_PDE_PTE;
> +
>                 }
>         } else
>                 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
> --
> 2.7.4
>
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