[PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels

[Deucher, Alexander]

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan at amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels
> 

Add a better patch description.  Something like:
Add query for sclk and mclk to the sysfs interface.

> Change-Id: I40fa698cd9a25df43aa4bf476c4aa0a8b043edf9
> Signed-off-by: Evan Quan <evan.quan at amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 48
> +++++++++++++++++++++++++-
>  1 file changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index a20a6fe..5135328 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -619,7 +619,53 @@ static int rv_force_clock_level(struct pp_hwmgr
> *hwmgr,
>  static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>  		enum pp_clock_type type, char *buf)
>  {
> -	return 0;
> +	struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
> +	struct rv_voltage_dependency_table *mclk_table =
> +			data->clock_vol_info.vdd_dep_on_fclk;
> +	int i, now, size = 0;
> +
> +	switch (type) {
> +	case PP_SCLK:
> +
> 	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> +				PPSMC_MSG_GetGfxclkFrequency),
> +				"Attempt to get current GFXCLK Failed!",
> +				return -1);
> +		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr-
> >smumgr,
> +				&now),
> +				"Attempt to get current GFXCLK Failed!",
> +				return -1);
> +
> +		size += sprintf(buf + size, "0: %uMhz %s\n",
> +				data->gfx_min_freq_limit / 100,
> +				((data->gfx_min_freq_limit / 100)
> +				 == now) ? "*" : "");
> +		size += sprintf(buf + size, "1: %uMhz %s\n",
> +				data->gfx_max_freq_limit / 100,
> +				((data->gfx_max_freq_limit / 100)
> +				 == now) ? "*" : "");
> +		break;
> +	case PP_MCLK:
> +
> 	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> +				PPSMC_MSG_GetFclkFrequency),
> +				"Attempt to get current MEMCLK Failed!",
> +				return -1);
> +		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr-
> >smumgr,
> +				&now),
> +				"Attempt to get current MEMCLK Failed!",
> +				return -1);

Return proper error codes in this function.

With the above comments fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> +
> +		for (i = 0; i < mclk_table->count; i++)
> +			size += sprintf(buf + size, "%d: %uMhz %s\n",
> +					i,
> +					mclk_table->entries[i].clk / 100,
> +					((mclk_table->entries[i].clk / 100)
> +					 == now) ? "*" : "");
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return size;
>  }
> 
>  static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct
> pp_hw_power_state *state,
> --
> 2.7.4