[PATCH] drm/amd/powerplay: implement pp_dpm_sclk sysfs interface on Vega12

Alex Deucher alexdeucher at gmail.com
Wed Apr 4 18:12:42 UTC 2018


On Wed, Apr 4, 2018 at 4:33 AM, Kenneth Feng <kenneth.feng at amd.com> wrote:
> Change-Id: Icd8f1a9bb9ef4bbd439f5eb5febd1d624b06bbd2
> Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>

Please include a proper patch description.  E.g.,

Replace forced sclk stubs with a proper implementation.

With that added:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 27 +++++++++++++++++-----
>  1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 6a85238..caeabda 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1742,13 +1742,28 @@ static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
>                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
>                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
>
> -               PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
> -                       "Failed to upload boot level to lowest!",
> -                       return -EINVAL);
> +               if (data->smc_state_table.gfx_boot_level !=
> +                               data->dpm_table.gfx_table.dpm_state.soft_min_level) {
> +                       PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
> +                               PPSMC_MSG_SetSoftMinByFreq,
> +                               PP_SCLK<<16 | data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_boot_level].value) == 0,
> +                               "Failed to upload boot level to lowest!", return -EINVAL);
> +                       data->dpm_table.gfx_table.dpm_state.soft_min_level =
> +                                       data->smc_state_table.gfx_boot_level;
> +
> +               }
> +
> +               if (data->smc_state_table.gfx_max_level !=
> +                       data->dpm_table.gfx_table.dpm_state.soft_max_level) {
> +                       PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
> +                               PPSMC_MSG_SetSoftMaxByFreq,
> +                               /* plus the vale by 1 to align the resolution */
> +                               PP_SCLK<<16 | (data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_max_level].value + 1)) == 0,
> +                               "Failed to upload dpm max level to highest!", return -EINVAL);
> +                       data->dpm_table.gfx_table.dpm_state.soft_max_level =
> +                                       data->smc_state_table.gfx_max_level;
> +               }
>
> -               PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
> -                       "Failed to upload dpm max level to highest!",
> -                       return -EINVAL);
>                 break;
>
>         case PP_MCLK:
> --
> 2.7.4
>
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