[PATCH 2/2] Revert "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)"

[S, Shirish]

Hi Harry, Alex,

The solution given while reviewing my patch was that "DC should support enabling a CRTC without a framebuffer."

Since the revert is a temporary workaround to address issue at hand and considering the bigger regression it will cause on ChromeOS(explained below),
I would strongly recommend that the revert should not be mainlined (to linus tree), until a proper fix for both the issues i.e., flickering and BUG hit on atomic is found.

For the sake of everyone's understanding in the list below is a brief background.

Mainline patch from intel folks, "846c7df drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2." 
introduces a slight behavioral change to rmfb. Instead of disabling a crtc when the primary plane is disabled, it now preserves it.

This change leads to BUG hit while performing atomic commit on amd driver leading to reboot/system instability on ChromeOS which has enabled
drm atomic way of rendering, I also remember it causing some issue on other OS as well.

Thanks & Regards,
Shirish S

-----Original Message-----
From: Michel Dänzer [mailto:michel at daenzer.net] 
Sent: Thursday, April 12, 2018 8:39 PM
To: Wentland, Harry <Harry.Wentland at amd.com>
Cc: amd-gfx at lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher at amd.com>; S, Shirish <Shirish.S at amd.com>
Subject: Re: [PATCH 2/2] Revert "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)"

On 2018-04-12 04:51 PM, Harry Wentland wrote:
> This seems to cause flickering and lock-ups for a wide range of users.
> Revert until we've found a proper fix for the flickering and lock-ups.
> 
> This reverts commit 36cc549d59864b7161f0e23d710c1c4d1b9cf022.
> 
> Cc: Shirish S <shirish.s at amd.com>
> Cc: Alex Deucher <alexander.deucher at amd.com>
> Cc: stable at vger.kernel.org
> Signed-off-by: Harry Wentland <harry.wentland at amd.com>

Thanks Harry, both patches are

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>


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