[PATCH 1/2] drm/amd/pp: Adding set_watermarks_for_clocks_ranges for SMU10

[Deucher, Alexander]

Series is:

Acked-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of mikita.lipski at amd.com <mikita.lipski at amd.com>
Sent: Monday, April 16, 2018 11:22:46 AM
To: amd-gfx at lists.freedesktop.org; Wentland, Harry; Zhu, Rex; Deucher, Alexander
Cc: Lipski, Mikita
Subject: [PATCH 1/2] drm/amd/pp: Adding set_watermarks_for_clocks_ranges for SMU10

From: Mikita Lipski <mikita.lipski at amd.com>

The function is never implemented for raven on linux.
It follows similair implementation as on windows.

SMU still needs to notify SMC and copy WM table, which is added
here. But on other Asics such as Vega this step is not implemented.

Signed-off-by: Mikita Lipski <mikita.lipski at amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 13 +++++++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 6ba3b1f..b712d16 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -992,6 +992,18 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
         return ret;
 }

+static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+{
+       struct smu10_hwmgr *data = hwmgr->backend;
+       Watermarks_t *table = &(data->water_marks_table);
+       int result = 0;
+
+       smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
+       smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
+       data->water_marks_exist = true;
+       return result;
+}
 static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
 {
         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
@@ -1021,6 +1033,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
         .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
         .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
         .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
+       .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
         .get_max_high_clocks = smu10_get_max_high_clocks,
         .read_sensor = smu10_read_sensor,
         .set_active_display_count = smu10_set_active_display_count,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
index 175c3a5..f68b218 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
@@ -290,6 +290,7 @@ struct smu10_hwmgr {
         bool                           vcn_dpg_mode;

         bool                           gfx_off_controled_by_driver;
+       bool                           water_marks_exist;
         Watermarks_t                      water_marks_table;
         struct smu10_clock_voltage_information   clock_vol_info;
         DpmClocks_t                       clock_table;
--
2.7.4

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