[PATCH] drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV

[Christian König]

> Does this actually work on SR-IOV? Or does it just seem to but nothing 
> bad happens because we get a GPU reset on a world switch?
I honestly don't know. I think that SR-IOV uses a specialized firmware 
where this packet has a different meaning.

But the real fix would be to get the RLC firmware fix to not 
reinitialize those regs to zero on world switch.

Christian.

Am 17.04.2018 um 16:02 schrieb Deucher, Alexander:
>
> Does this actually work on SR-IOV?  Or does it just seem to but 
> nothing bad happens because we get a GPU reset on a world switch?  The 
> behavior of this packet should be the same as SDMA and that definitely 
> doesn't work.  I don't see why this would be any different.
>
>
> Acked-by: Alex Deucher <alexander.deucher at amd.com>
>
>
> Alex
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of 
> Christian König <ckoenig.leichtzumerken at gmail.com>
> *Sent:* Tuesday, April 17, 2018 9:01:35 AM
> *To:* amd-gfx at lists.freedesktop.org
> *Subject:* [PATCH] drm/amdgpu: limit reg_write_reg_wait workaround to 
> SRIOV
> Turned out that this locks up some bare metal Vega10.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 583f6f616dd3..5329d7e5fb71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4144,7 +4144,12 @@ static void 
> gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
>  {
>          int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
>
> -       gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, 
> mask, 0x20);
> +       if (amdgpu_sriov_vf(adev))
> +               gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
> +                                     ref, mask, 0x20);
> +       else
> + amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
> + ref, mask);
>  }
>
>  static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device 
> *adev,
> -- 
> 2.14.1
>
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