[PATCH] drm/amd/pp: Print out voltage/clock range in sysfs

[Alex Deucher]

On Wed, Apr 18, 2018 at 10:50 PM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> when user cat pp_od_clk_voltage
> add display info about the sclk/mclk/vddc range that user can overdrive
> as:
> OD_SCLK:
> 0:        300MHz        900 mV
> 1:        400MHz        912 mV
> 2:        500MHz        925 mV
> 3:        600MHz        937 mV
> 4:        700MHz        950 mV
> 5:        800MHz        975 mV
> 6:        900MHz        987 mV
> 7:       1000MHz       1000 mV
> OD_MCLK:
> 0:        300MHz        900 mV
> 1:       1500MHz        912 mV
> OD_RANGE:
> SCLK:     300MHz       1200MHz
> MCLK:     300MHz       1500MHz
> VDDC:     700mV        1200mV
>
> also
> 1. remove unnecessary whitespace before a quoted newline
> 2. change unit of frequency Mhz to MHz

While you are here, you could also make the spacing consistent between
the values and the units.  e.g.,
300MHz vs 300 MHz
or
700mV vs 700 mV

Either way:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c           |  1 +
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h   |  1 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 22 ++++++++++++++++++----
>  3 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 744f105..8f968bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -437,6 +437,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
>         if (adev->powerplay.pp_funcs->print_clock_levels) {
>                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
>                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
> +               size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
>                 return size;
>         } else {
>                 return snprintf(buf, PAGE_SIZE, "\n");
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 01969b1..06f08f3 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -94,6 +94,7 @@ enum pp_clock_type {
>         PP_PCIE,
>         OD_SCLK,
>         OD_MCLK,
> +       OD_RANGE,
>  };
>
>  enum amd_pp_sensors {
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 966b5b1..df8fa99 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4335,22 +4335,36 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>                 break;
>         case OD_SCLK:
>                 if (hwmgr->od_enabled) {
> -                       size = sprintf(buf, "%s: \n", "OD_SCLK");
> +                       size = sprintf(buf, "%s:\n", "OD_SCLK");
>                         for (i = 0; i < odn_sclk_table->num_of_pl; i++)
> -                               size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
> +                               size += sprintf(buf + size, "%d: %10uMHz %10u mV\n",
>                                         i, odn_sclk_table->entries[i].clock / 100,
>                                         odn_sclk_table->entries[i].vddc);
>                 }
>                 break;
>         case OD_MCLK:
>                 if (hwmgr->od_enabled) {
> -                       size = sprintf(buf, "%s: \n", "OD_MCLK");
> +                       size = sprintf(buf, "%s:\n", "OD_MCLK");
>                         for (i = 0; i < odn_mclk_table->num_of_pl; i++)
> -                               size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
> +                               size += sprintf(buf + size, "%d: %10uMHz %10u mV\n",
>                                         i, odn_mclk_table->entries[i].clock / 100,
>                                         odn_mclk_table->entries[i].vddc);
>                 }
>                 break;
> +       case OD_RANGE:
> +               if (hwmgr->od_enabled) {
> +                       size = sprintf(buf, "%s:\n", "OD_RANGE");
> +                       size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
> +                               data->golden_dpm_table.sclk_table.dpm_levels[0].value / 100,
> +                               hwmgr->platform_descriptor.overdriveLimit.engineClock / 100);
> +                       size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
> +                               data->golden_dpm_table.mclk_table.dpm_levels[0].value / 100,
> +                               hwmgr->platform_descriptor.overdriveLimit.memoryClock / 100);
> +                       size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
> +                               data->odn_dpm_table.min_vddc,
> +                               data->odn_dpm_table.max_vddc);
> +               }
> +               break;
>         default:
>                 break;
>         }
> --
> 1.9.1
>
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