[PATCH] drm/amd/pp: Reset memory levels table before populating values

[Nicholas Kazlauskas]

[Why]

On POLARIS10 powerplay can fail to retrieve minimum memory clocks.
This cascades into failing to find the MinVddc value when
populating a single memory level. When this is called during
polaris10_populate_all_memory_levels the function exits early leaving
the previously used values in the smc_state_table.

Under these conditions visual corruption can be observed on the screen
during modesets between specific bandwidth thresholds.

[How]

There seems to be a similar problem and solution for Tonga: a memset
on the levels table before populating its values. This change fixes
the visual corruption that seems to occur when changing from a low
clock mode (640x480 at 75Hz) to a medium clock mode (1920x1200 at 60Hz).

However, this is a small fix for a symptom of the larger issue of
failing to find the MinVddc. Other hardware would seem to encounter
the same issue if the table is empty, so significant refactoring
would likely be needed.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
---
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 1276f168ff68..68356479dac1 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -1134,6 +1134,8 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 			smu_data->smc_state_table.MemoryLevel;
 	uint32_t i;
 
+	memset(levels, 0, array_size);
+
 	for (i = 0; i < dpm_table->mclk_table.count; i++) {
 		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
 				"can not populate memory level as memory clock is zero",
-- 
2.17.1