[PATCH 4/9] drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr
Zhu, Rex
Rex.Zhu at amd.com
Thu Dec 6 14:48:44 UTC 2018
Hi Christian,
We allocate and map csa per ctx, need to record the used/free vm space.
So use bitmap to manager the reserved vm space.
Also add resv_space_id in ctx.
When amdgpu_ctx_fini, we can clear the bit in the bitmap.
Best Regards
Rex
> -----Original Message-----
> From: Christian König <ckoenig.leichtzumerken at gmail.com>
> Sent: Thursday, December 6, 2018 8:34 PM
> To: Zhu, Rex <Rex.Zhu at amd.com>; amd-gfx at lists.freedesktop.org
> Subject: Re: [PATCH 4/9] drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr
>
> Am 06.12.18 um 13:14 schrieb Rex Zhu:
> > used to manager the reserverd vm space.
>
> Why do we need that?
>
> Christian.
>
> >
> > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 ++++++--
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++++-
> > 3 files changed, 14 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > index 8edf54b..8802ff2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > @@ -529,10 +529,14 @@ int amdgpu_ctx_wait_prev_fence(struct
> amdgpu_ctx *ctx,
> > return 0;
> > }
> >
> > -void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
> > +int amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
> > {
> > mutex_init(&mgr->lock);
> > idr_init(&mgr->ctx_handles);
> > + mgr->resv_vm_bitmap =
> kzalloc(DIV_ROUND_UP(AMDGPU_VM_MAX_NUM_CTX, BITS_PER_BYTE),
> GFP_KERNEL);
> > + if (unlikely(!mgr->resv_vm_bitmap))
> > + return -ENOMEM;
> > + return 0;
> > }
> >
> > void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr) @@
> > -601,7 +605,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
> *mgr)
> > if (kref_put(&ctx->refcount, amdgpu_ctx_fini) != 1)
> > DRM_ERROR("ctx %p is still alive\n", ctx);
> > }
> > -
> > + kfree(mgr->resv_vm_bitmap);
> > idr_destroy(&mgr->ctx_handles);
> > mutex_destroy(&mgr->lock);
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > index b3b012c..94ac951 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > @@ -38,6 +38,7 @@ struct amdgpu_ctx_entity {
> > struct amdgpu_ctx {
> > struct kref refcount;
> > struct amdgpu_device *adev;
> > +
> > unsigned reset_counter;
> > unsigned reset_counter_query;
> > uint32_t vram_lost_counter;
> > @@ -56,6 +57,7 @@ struct amdgpu_ctx_mgr {
> > struct mutex lock;
> > /* protected by lock */
> > struct idr ctx_handles;
> > + unsigned long *resv_vm_bitmap;
> > };
> >
> > extern const unsigned int
> amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
> > @@ -80,7 +82,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void
> *data,
> > int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
> > struct drm_sched_entity *entity);
> >
> > -void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
> > +int amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
> > void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
> > void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr);
> > void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index 52e4e90..338a091 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -988,11 +988,15 @@ int amdgpu_driver_open_kms(struct drm_device
> *dev, struct drm_file *file_priv)
> > mutex_init(&fpriv->bo_list_lock);
> > idr_init(&fpriv->bo_list_handles);
> >
> > - amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
> > + if (amdgpu_ctx_mgr_init(&fpriv->ctx_mgr))
> > + goto error_ctx_mgr;
> >
> > file_priv->driver_priv = fpriv;
> > goto out_suspend;
> >
> > +error_ctx_mgr:
> > + idr_destroy(&fpriv->bo_list_handles);
> > + mutex_destroy(&fpriv->bo_list_lock);
> > error_vm:
> > amdgpu_vm_fini(adev, &fpriv->vm);
> >
More information about the amd-gfx
mailing list