[PATCH 29/45] drm/amd/display: Use 100 Hz precision for pipe pixel clocks
Christian König
ckoenig.leichtzumerken at gmail.com
Wed Dec 12 08:19:10 UTC 2018
Am 11.12.18 um 23:57 schrieb sunpeng.li at amd.com:
> From: Ken Chalmers <ken.chalmers at amd.com>
>
> [Why]
> Users would like more accurate pixel clocks, especially for fractional
> "TV" frame rates like 59.94 Hz.
>
> [How]
> Store and communicate pixel clocks with 100 Hz accuracy from
> dc_crtc_timing through to BIOS command table setpixelclock call.
Why not directly use Hz?
I mean we don't have any pixel clocks above 4GHz, don't we? So a 32bit
integer should be a perfect fit.
Christian.
>
> Signed-off-by: Ken Chalmers <ken.chalmers at amd.com>
> Reviewed-by: Charlene Liu <Charlene.Liu at amd.com>
> Acked-by: Leo Li <sunpeng.li at amd.com>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +-
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
> .../gpu/drm/amd/display/dc/bios/command_table.c | 19 +-
> .../gpu/drm/amd/display/dc/bios/command_table2.c | 6 +-
> drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 10 +-
> drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 10 +-
> drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +--
> drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 +-
> drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 +-
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 10 +-
> drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +-
> drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
> drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 12 +-
> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 196 ++++++++++-----------
> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 6 +-
> .../drm/amd/display/dc/dce/dce_stream_encoder.c | 4 +-
> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 20 +--
> .../drm/amd/display/dc/dce110/dce110_resource.c | 10 +-
> .../amd/display/dc/dce80/dce80_timing_generator.c | 8 +-
> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
> .../display/dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
> .../drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 18 +-
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 2 +-
> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +-
> .../amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
> drivers/gpu/drm/amd/display/dc/inc/clock_source.h | 8 +-
> .../drm/amd/display/include/bios_parser_types.h | 4 +-
> .../drm/amd/display/modules/freesync/freesync.c | 12 +-
> 29 files changed, 206 insertions(+), 209 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index c0c664e..23bb49e 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2554,7 +2554,7 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
> * according to HDMI spec, we use YCbCr709 and YCbCr601
> * respectively
> */
> - if (dc_crtc_timing->pix_clk_khz > 27030) {
> + if (dc_crtc_timing->pix_clk_100hz > 270300) {
> if (dc_crtc_timing->flags.Y_ONLY)
> color_space =
> COLOR_SPACE_YCBCR709_LIMITED;
> @@ -2597,7 +2597,7 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
> if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> return;
> do {
> - normalized_clk = timing_out->pix_clk_khz;
> + normalized_clk = timing_out->pix_clk_100hz / 10;
> /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
> if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> normalized_clk /= 2;
> @@ -2678,7 +2678,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
> mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
> timing_out->v_sync_width =
> mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
> - timing_out->pix_clk_khz = mode_in->crtc_clock;
> + timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
> timing_out->aspect_ratio = get_aspect_ratio(mode_in);
>
> stream->output_color_space = get_output_color_space(timing_out);
> @@ -2806,7 +2806,7 @@ static void set_master_stream(struct dc_stream_state *stream_set[],
> if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
> int refresh_rate = 0;
>
> - refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
> + refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
> (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
> if (refresh_rate > highest_rfr) {
> highest_rfr = refresh_rate;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index b0bc831..e6ab018 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -205,7 +205,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
> mst_port = aconnector->port;
>
> if (enable) {
> - clock = stream->timing.pix_clk_khz;
> + clock = stream->timing.pix_clk_100hz / 10;
>
> switch (stream->timing.display_color_depth) {
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> index 2bd7cd9..67c119b 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> @@ -964,9 +964,9 @@ static enum bp_result set_pixel_clock_v3(
> allocation.sPCLKInput.ucPostDiv =
> (uint8_t)bp_params->pixel_clock_post_divider;
>
> - /* We need to convert from KHz units into 10KHz units */
> + /* We need to convert from 100Hz units into 10KHz units */
> allocation.sPCLKInput.usPixelClock =
> - cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
> + cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
>
> params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput;
> params->ucTransmitterId =
> @@ -1042,9 +1042,9 @@ static enum bp_result set_pixel_clock_v5(
> (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
> bp_params->signal_type, false);
>
> - /* We need to convert from KHz units into 10KHz units */
> + /* We need to convert from 100Hz units into 10KHz units */
> clk.sPCLKInput.usPixelClock =
> - cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
> + cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
>
> if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
> clk.sPCLKInput.ucMiscInfo |=
> @@ -1118,9 +1118,9 @@ static enum bp_result set_pixel_clock_v6(
> (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
> bp_params->signal_type, false);
>
> - /* We need to convert from KHz units into 10KHz units */
> + /* We need to convert from 100 Hz units into 10KHz units */
> clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =
> - cpu_to_le32(bp_params->target_pixel_clock / 10);
> + cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
>
> if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
> clk.sPCLKInput.ucMiscInfo |=
> @@ -1182,8 +1182,7 @@ static enum bp_result set_pixel_clock_v7(
> clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
> clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
>
> - /* We need to convert from KHz units into 10KHz units */
> - clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock * 10);
> + clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock_100hz);
>
> clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
>
> @@ -2164,7 +2163,7 @@ static enum bp_result program_clock_v5(
> /* We need to convert from KHz units into 10KHz units */
> params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;
> params.sPCLKInput.usPixelClock =
> - cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
> + cpu_to_le16((uint16_t) (bp_params->target_pixel_clock_100hz / 100));
> params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;
>
> if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
> @@ -2196,7 +2195,7 @@ static enum bp_result program_clock_v6(
> /* We need to convert from KHz units into 10KHz units */
> params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;
> params.sPCLKInput.ulDispEngClkFreq =
> - cpu_to_le32(bp_params->target_pixel_clock / 10);
> + cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
>
> if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
> params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> index 2b5dc49..7d3e577 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> @@ -301,9 +301,7 @@ static enum bp_result set_pixel_clock_v7(
> cmd_helper->encoder_mode_bp_to_atom(
> bp_params->signal_type, false);
>
> - /* We need to convert from KHz units into 10KHz units */
> - clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock *
> - 10);
> + clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock_100hz);
>
> clk.deep_color_ratio =
> (uint8_t) bp->cmd_helper->
> @@ -311,7 +309,7 @@ static enum bp_result set_pixel_clock_v7(
> bp_params->color_depth);
> DC_LOG_BIOS("%s:program display clock = %d"\
> "colorDepth = %d\n", __func__,\
> - bp_params->target_pixel_clock, bp_params->color_depth);
> + bp_params->target_pixel_clock_100hz, bp_params->color_depth);
>
> if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
> clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> index 9ebe30b..f3aa7b5 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> @@ -2792,7 +2792,7 @@ static void populate_initial_data(
> data->lpt_en[num_displays + 4] = false;
> data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
> data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
> - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
> + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000);
> data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
> data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
> data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
> @@ -2881,7 +2881,7 @@ static void populate_initial_data(
>
> /* Pipes without underlay after */
> for (i = 0; i < pipe_count; i++) {
> - unsigned int pixel_clock_khz;
> + unsigned int pixel_clock_100hz;
> if (!pipe[i].stream || pipe[i].bottom_pipe)
> continue;
>
> @@ -2890,10 +2890,10 @@ static void populate_initial_data(
> data->lpt_en[num_displays + 4] = false;
> data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
> data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
> - pixel_clock_khz = pipe[i].stream->timing.pix_clk_khz;
> + pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz;
> if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
> - pixel_clock_khz *= 2;
> - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pixel_clock_khz, 1000);
> + pixel_clock_100hz *= 2;
> + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pixel_clock_100hz, 10000);
> if (pipe[i].plane_state) {
> data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
> data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 446ee48..12d1842 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -416,7 +416,7 @@ static void pipe_ctx_to_e2e_pipe_params (
> - pipe->stream->timing.v_addressable
> - pipe->stream->timing.v_border_bottom
> - pipe->stream->timing.v_border_top;
> - input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
> + input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
> input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
> input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
> input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
> @@ -663,9 +663,9 @@ static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
> }
>
> static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
> - unsigned int pixel_rate_khz)
> + unsigned int pixel_rate_100hz)
> {
> - float pixel_rate_mhz = pixel_rate_khz / 1000;
> + float pixel_rate_mhz = pixel_rate_100hz / 10000;
>
> /*
> * force enabling pipe split by lower dpp clock for DPM0 to just
> @@ -688,7 +688,7 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
>
> if (context->stream_count == 1 &&
> dbg->force_single_disp_pipe_split)
> - hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_khz);
> + hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
> }
>
> bool dcn_validate_bandwidth(
> @@ -845,7 +845,7 @@ bool dcn_validate_bandwidth(
> v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
> - v->vactive[input_idx]
> - pipe->stream->timing.v_front_porch;
> - v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz/1000.0;
> + v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
> if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
> v->pixel_clock[input_idx] *= 2;
> if (!pipe->plane_state) {
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index c98fa8d..764a7bf 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -1083,7 +1083,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
> context->streams[i]->timing.v_addressable,
> context->streams[i]->timing.h_total,
> context->streams[i]->timing.v_total,
> - context->streams[i]->timing.pix_clk_khz);
> + context->streams[i]->timing.pix_clk_100hz / 10);
> }
>
> dc_enable_stereo(dc, context, dc_streams, context->stream_count);
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 69bee01..a87db7a 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1934,7 +1934,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
> && (stream->timing.v_addressable == 480);
>
> if (stream->phy_pix_clk == 0)
> - stream->phy_pix_clk = stream->timing.pix_clk_khz;
> + stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
> if (stream->phy_pix_clk > 340000)
> is_over_340mhz = true;
>
> @@ -1988,7 +1988,7 @@ static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
> struct dc_link *link = stream->link;
>
> if (stream->phy_pix_clk == 0)
> - stream->phy_pix_clk = stream->timing.pix_clk_khz;
> + stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
>
> memset(&stream->link->cur_link_settings, 0,
> sizeof(struct dc_link_settings));
> @@ -2063,7 +2063,7 @@ static bool dp_active_dongle_validate_timing(
> const struct dc_crtc_timing *timing,
> const struct dpcd_caps *dpcd_caps)
> {
> - unsigned int required_pix_clk = timing->pix_clk_khz;
> + unsigned int required_pix_clk_100hz = timing->pix_clk_100hz;
> const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
>
> switch (dpcd_caps->dongle_type) {
> @@ -2103,9 +2103,9 @@ static bool dp_active_dongle_validate_timing(
>
> /* Check Color Depth and Pixel Clock */
> if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> - required_pix_clk /= 2;
> + required_pix_clk_100hz /= 2;
> else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
> - required_pix_clk = required_pix_clk * 2 / 3;
> + required_pix_clk_100hz = required_pix_clk_100hz * 2 / 3;
>
> switch (timing->display_color_depth) {
> case COLOR_DEPTH_666:
> @@ -2115,12 +2115,12 @@ static bool dp_active_dongle_validate_timing(
> case COLOR_DEPTH_101010:
> if (dongle_caps->dp_hdmi_max_bpc < 10)
> return false;
> - required_pix_clk = required_pix_clk * 10 / 8;
> + required_pix_clk_100hz = required_pix_clk_100hz * 10 / 8;
> break;
> case COLOR_DEPTH_121212:
> if (dongle_caps->dp_hdmi_max_bpc < 12)
> return false;
> - required_pix_clk = required_pix_clk * 12 / 8;
> + required_pix_clk_100hz = required_pix_clk_100hz * 12 / 8;
> break;
>
> case COLOR_DEPTH_141414:
> @@ -2130,7 +2130,7 @@ static bool dp_active_dongle_validate_timing(
> return false;
> }
>
> - if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
> + if (required_pix_clk_100hz > (dongle_caps->dp_hdmi_max_pixel_clk * 10))
> return false;
>
> return true;
> @@ -2141,7 +2141,7 @@ enum dc_status dc_link_validate_mode_timing(
> struct dc_link *link,
> const struct dc_crtc_timing *timing)
> {
> - uint32_t max_pix_clk = stream->link->dongle_max_pix_clk;
> + uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
> struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
>
> /* A hack to avoid failing any modes for EDID override feature on
> @@ -2151,7 +2151,7 @@ enum dc_status dc_link_validate_mode_timing(
> return DC_OK;
>
> /* Passive Dongle */
> - if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
> + if (0 != max_pix_clk && timing->pix_clk_100hz > max_pix_clk)
> return DC_EXCEED_DONGLE_CAP;
>
> /* Active Dongle*/
> @@ -2301,7 +2301,7 @@ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
> uint32_t denominator;
>
> bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
> - kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
> + kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 * bpc * 3;
>
> /*
> * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index f40271e..56a06bb 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -1419,7 +1419,7 @@ static uint32_t bandwidth_in_kbps_from_timing(
>
> ASSERT(bits_per_channel != 0);
>
> - kbps = timing->pix_clk_khz;
> + kbps = timing->pix_clk_100hz / 10;
> kbps *= bits_per_channel;
>
> if (timing->flags.Y_ONLY != 1) {
> @@ -1461,7 +1461,7 @@ bool dp_validate_mode_timing(
> const struct dc_link_settings *link_setting;
>
> /*always DP fail safe mode*/
> - if (timing->pix_clk_khz == (uint32_t) 25175 &&
> + if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
> timing->h_addressable == (uint32_t) 640 &&
> timing->v_addressable == (uint32_t) 480)
> return true;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> index f8af776..f96fab3 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> @@ -74,8 +74,8 @@ void dp_enable_link_phy(
> if (pipes[i].clock_source != NULL &&
> pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
> pipes[i].clock_source = dp_cs;
> - pipes[i].stream_res.pix_clk_params.requested_pix_clk =
> - pipes[i].stream->timing.pix_clk_khz;
> + pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
> + pipes[i].stream->timing.pix_clk_100hz;
> pipes[i].clock_source->funcs->program_pix_clk(
> pipes[i].clock_source,
> &pipes[i].stream_res.pix_clk_params,
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index cee712a..33fd88d 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -351,8 +351,8 @@ bool resource_are_streams_timing_synchronizable(
> != stream2->timing.v_addressable)
> return false;
>
> - if (stream1->timing.pix_clk_khz
> - != stream2->timing.pix_clk_khz)
> + if (stream1->timing.pix_clk_100hz
> + != stream2->timing.pix_clk_100hz)
> return false;
>
> if (stream1->clamping.c_depth != stream2->clamping.c_depth)
> @@ -1755,7 +1755,7 @@ static struct dc_stream_state *find_pll_sharable_stream(
>
> static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
> {
> - uint32_t pix_clk = timing->pix_clk_khz;
> + uint32_t pix_clk = timing->pix_clk_100hz;
> uint32_t normalized_pix_clk = pix_clk;
>
> if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> @@ -1787,10 +1787,10 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream)
> /* update actual pixel clock on all streams */
> if (dc_is_hdmi_signal(stream->signal))
> stream->phy_pix_clk = get_norm_pix_clk(
> - &stream->timing);
> + &stream->timing) / 10;
> else
> stream->phy_pix_clk =
> - stream->timing.pix_clk_khz;
> + stream->timing.pix_clk_100hz / 10;
>
> if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
> stream->phy_pix_clk *= 2;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> index ed5eb8a..996298c 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> @@ -44,7 +44,7 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
>
> if (dc_is_dvi_signal(stream->signal)) {
> if (stream->ctx->dc->caps.dual_link_dvi &&
> - stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK &&
> + (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
> sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
> stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
> else
> @@ -361,7 +361,7 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
> stream->output_color_space);
> DC_LOG_DC(
> "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
> - stream->timing.pix_clk_khz,
> + stream->timing.pix_clk_100hz / 10,
> stream->timing.h_total,
> stream->timing.v_total,
> stream->timing.pixel_encoding,
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
> index 9ddfe4c..e69c9cc 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
> @@ -730,7 +730,7 @@ struct dc_crtc_timing {
> uint32_t v_front_porch;
> uint32_t v_sync_width;
>
> - uint32_t pix_clk_khz;
> + uint32_t pix_clk_100hz;
>
> uint32_t vic;
> uint32_t hdmi_vic;
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
> index 5c1a7c0..8940430 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
> @@ -194,8 +194,8 @@ static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)
> if (pipe_ctx->top_pipe)
> continue;
>
> - if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
> - max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
> + if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
> + max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
>
> /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
> * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
> @@ -257,7 +257,7 @@ static int dce_set_clock(
> clk_mgr_dce->dentist_vco_freq_khz / 64);
>
> /* Prepare to program display clock*/
> - pxl_clk_params.target_pixel_clock = requested_clk_khz;
> + pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
> pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
>
> if (clk_mgr_dce->dfs_bypass_active)
> @@ -494,7 +494,7 @@ void dce110_fill_display_configs(
> stream->link->cur_link_settings.link_spread;
> cfg->sym_clock = stream->phy_pix_clk;
> /* Round v_refresh*/
> - cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
> + cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
> cfg->v_refresh /= stream->timing.h_total;
> cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
> / stream->timing.v_total;
> @@ -518,7 +518,7 @@ static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
> - stream->timing.v_addressable);
>
> vertical_blank_time = vertical_blank_in_pixels
> - * 1000 / stream->timing.pix_clk_khz;
> + * 10000 / stream->timing.pix_clk_100hz;
>
> if (min_vertical_blank_time > vertical_blank_time)
> min_vertical_blank_time = vertical_blank_time;
> @@ -612,7 +612,7 @@ static void dce11_pplib_apply_display_requirements(
>
> pp_display_cfg->crtc_index =
> pp_display_cfg->disp_configs[0].pipe_idx;
> - pp_display_cfg->line_time_in_us = timing->h_total * 1000 / timing->pix_clk_khz;
> + pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
> }
>
> if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index 723ce80..c67e90e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -108,28 +108,28 @@ static const struct spread_spectrum_data *get_ss_data_entry(
> }
>
> /**
> -* Function: calculate_fb_and_fractional_fb_divider
> -*
> -* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
> -*
> -*PARAMETERS:
> -* targetPixelClock Desired frequency in 10 KHz
> -* ref_divider Reference divider (already known)
> -* postDivider Post Divider (already known)
> -* feedback_divider_param Pointer where to store
> -* calculated feedback divider value
> -* fract_feedback_divider_param Pointer where to store
> -* calculated fract feedback divider value
> -*
> -*RETURNS:
> -* It fills the locations pointed by feedback_divider_param
> -* and fract_feedback_divider_param
> -* It returns - true if feedback divider not 0
> -* - false should never happen)
> -*/
> + * Function: calculate_fb_and_fractional_fb_divider
> + *
> + * * DESCRIPTION: Calculates feedback and fractional feedback dividers values
> + *
> + *PARAMETERS:
> + * targetPixelClock Desired frequency in 100 Hz
> + * ref_divider Reference divider (already known)
> + * postDivider Post Divider (already known)
> + * feedback_divider_param Pointer where to store
> + * calculated feedback divider value
> + * fract_feedback_divider_param Pointer where to store
> + * calculated fract feedback divider value
> + *
> + *RETURNS:
> + * It fills the locations pointed by feedback_divider_param
> + * and fract_feedback_divider_param
> + * It returns - true if feedback divider not 0
> + * - false should never happen)
> + */
> static bool calculate_fb_and_fractional_fb_divider(
> struct calc_pll_clock_source *calc_pll_cs,
> - uint32_t target_pix_clk_khz,
> + uint32_t target_pix_clk_100hz,
> uint32_t ref_divider,
> uint32_t post_divider,
> uint32_t *feedback_divider_param,
> @@ -138,11 +138,11 @@ static bool calculate_fb_and_fractional_fb_divider(
> uint64_t feedback_divider;
>
> feedback_divider =
> - (uint64_t)target_pix_clk_khz * ref_divider * post_divider;
> + (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
> feedback_divider *= 10;
> /* additional factor, since we divide by 10 afterwards */
> feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
> - feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz);
> + feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
>
> /*Round to the number of precision
> * The following code replace the old code (ullfeedbackDivider + 5)/10
> @@ -195,36 +195,36 @@ static bool calc_fb_divider_checking_tolerance(
> {
> uint32_t feedback_divider;
> uint32_t fract_feedback_divider;
> - uint32_t actual_calculated_clock_khz;
> + uint32_t actual_calculated_clock_100hz;
> uint32_t abs_err;
> - uint64_t actual_calc_clk_khz;
> + uint64_t actual_calc_clk_100hz;
>
> calculate_fb_and_fractional_fb_divider(
> calc_pll_cs,
> - pll_settings->adjusted_pix_clk,
> + pll_settings->adjusted_pix_clk_100hz,
> ref_divider,
> post_divider,
> &feedback_divider,
> &fract_feedback_divider);
>
> /*Actual calculated value*/
> - actual_calc_clk_khz = (uint64_t)feedback_divider *
> + actual_calc_clk_100hz = (uint64_t)feedback_divider *
> calc_pll_cs->fract_fb_divider_factor +
> fract_feedback_divider;
> - actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
> - actual_calc_clk_khz =
> - div_u64(actual_calc_clk_khz,
> + actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10;
> + actual_calc_clk_100hz =
> + div_u64(actual_calc_clk_100hz,
> ref_divider * post_divider *
> calc_pll_cs->fract_fb_divider_factor);
>
> - actual_calculated_clock_khz = (uint32_t)(actual_calc_clk_khz);
> + actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
>
> - abs_err = (actual_calculated_clock_khz >
> - pll_settings->adjusted_pix_clk)
> - ? actual_calculated_clock_khz -
> - pll_settings->adjusted_pix_clk
> - : pll_settings->adjusted_pix_clk -
> - actual_calculated_clock_khz;
> + abs_err = (actual_calculated_clock_100hz >
> + pll_settings->adjusted_pix_clk_100hz)
> + ? actual_calculated_clock_100hz -
> + pll_settings->adjusted_pix_clk_100hz
> + : pll_settings->adjusted_pix_clk_100hz -
> + actual_calculated_clock_100hz;
>
> if (abs_err <= tolerance) {
> /*found good values*/
> @@ -233,10 +233,10 @@ static bool calc_fb_divider_checking_tolerance(
> pll_settings->feedback_divider = feedback_divider;
> pll_settings->fract_feedback_divider = fract_feedback_divider;
> pll_settings->pix_clk_post_divider = post_divider;
> - pll_settings->calculated_pix_clk =
> - actual_calculated_clock_khz;
> + pll_settings->calculated_pix_clk_100hz =
> + actual_calculated_clock_100hz;
> pll_settings->vco_freq =
> - actual_calculated_clock_khz * post_divider;
> + actual_calculated_clock_100hz * post_divider / 10;
> return true;
> }
> return false;
> @@ -257,8 +257,8 @@ static bool calc_pll_dividers_in_range(
>
> /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
> * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
> - tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /
> - 10000;
> + tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
> + 100000;
> if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
> tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
>
> @@ -294,7 +294,7 @@ static uint32_t calculate_pixel_clock_pll_dividers(
> uint32_t min_ref_divider;
> uint32_t max_ref_divider;
>
> - if (pll_settings->adjusted_pix_clk == 0) {
> + if (pll_settings->adjusted_pix_clk_100hz == 0) {
> DC_LOG_ERROR(
> "%s Bad requested pixel clock", __func__);
> return MAX_PLL_CALC_ERROR;
> @@ -306,21 +306,21 @@ static uint32_t calculate_pixel_clock_pll_dividers(
> max_post_divider = pll_settings->pix_clk_post_divider;
> } else {
> min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
> - if (min_post_divider * pll_settings->adjusted_pix_clk <
> - calc_pll_cs->min_vco_khz) {
> - min_post_divider = calc_pll_cs->min_vco_khz /
> - pll_settings->adjusted_pix_clk;
> + if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
> + calc_pll_cs->min_vco_khz * 10) {
> + min_post_divider = calc_pll_cs->min_vco_khz * 10 /
> + pll_settings->adjusted_pix_clk_100hz;
> if ((min_post_divider *
> - pll_settings->adjusted_pix_clk) <
> - calc_pll_cs->min_vco_khz)
> + pll_settings->adjusted_pix_clk_100hz) <
> + calc_pll_cs->min_vco_khz * 10)
> min_post_divider++;
> }
>
> max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
> - if (max_post_divider * pll_settings->adjusted_pix_clk
> - > calc_pll_cs->max_vco_khz)
> - max_post_divider = calc_pll_cs->max_vco_khz /
> - pll_settings->adjusted_pix_clk;
> + if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
> + > calc_pll_cs->max_vco_khz * 10)
> + max_post_divider = calc_pll_cs->max_vco_khz * 10 /
> + pll_settings->adjusted_pix_clk_100hz;
> }
>
> /* 2) Find Reference divider ranges
> @@ -392,47 +392,47 @@ static bool pll_adjust_pix_clk(
> struct pixel_clk_params *pix_clk_params,
> struct pll_settings *pll_settings)
> {
> - uint32_t actual_pix_clk_khz = 0;
> - uint32_t requested_clk_khz = 0;
> + uint32_t actual_pix_clk_100hz = 0;
> + uint32_t requested_clk_100hz = 0;
> struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
> 0 };
> enum bp_result bp_result;
> switch (pix_clk_params->signal_type) {
> case SIGNAL_TYPE_HDMI_TYPE_A: {
> - requested_clk_khz = pix_clk_params->requested_pix_clk;
> + requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
> if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
> switch (pix_clk_params->color_depth) {
> case COLOR_DEPTH_101010:
> - requested_clk_khz = (requested_clk_khz * 5) >> 2;
> + requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
> break; /* x1.25*/
> case COLOR_DEPTH_121212:
> - requested_clk_khz = (requested_clk_khz * 6) >> 2;
> + requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
> break; /* x1.5*/
> case COLOR_DEPTH_161616:
> - requested_clk_khz = requested_clk_khz * 2;
> + requested_clk_100hz = requested_clk_100hz * 2;
> break; /* x2.0*/
> default:
> break;
> }
> }
> - actual_pix_clk_khz = requested_clk_khz;
> + actual_pix_clk_100hz = requested_clk_100hz;
> }
> break;
>
> case SIGNAL_TYPE_DISPLAY_PORT:
> case SIGNAL_TYPE_DISPLAY_PORT_MST:
> case SIGNAL_TYPE_EDP:
> - requested_clk_khz = pix_clk_params->requested_sym_clk;
> - actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
> + requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
> + actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
> break;
>
> default:
> - requested_clk_khz = pix_clk_params->requested_pix_clk;
> - actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
> + requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
> + actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
> break;
> }
>
> - bp_adjust_pixel_clock_params.pixel_clock = requested_clk_khz;
> + bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
> bp_adjust_pixel_clock_params.
> encoder_object_id = pix_clk_params->encoder_object_id;
> bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
> @@ -441,9 +441,9 @@ static bool pll_adjust_pix_clk(
> bp_result = clk_src->bios->funcs->adjust_pixel_clock(
> clk_src->bios, &bp_adjust_pixel_clock_params);
> if (bp_result == BP_RESULT_OK) {
> - pll_settings->actual_pix_clk = actual_pix_clk_khz;
> - pll_settings->adjusted_pix_clk =
> - bp_adjust_pixel_clock_params.adjusted_pixel_clock;
> + pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
> + pll_settings->adjusted_pix_clk_100hz =
> + bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
> pll_settings->reference_divider =
> bp_adjust_pixel_clock_params.reference_divider;
> pll_settings->pix_clk_post_divider =
> @@ -490,7 +490,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
> const struct spread_spectrum_data *ss_data = get_ss_data_entry(
> clk_src,
> pix_clk_params->signal_type,
> - pll_settings->adjusted_pix_clk);
> + pll_settings->adjusted_pix_clk_100hz / 10);
>
> if (NULL != ss_data)
> pll_settings->ss_percentage = ss_data->percentage;
> @@ -502,13 +502,13 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
> * to continue. */
> DC_LOG_ERROR(
> "%s: Failed to adjust pixel clock!!", __func__);
> - pll_settings->actual_pix_clk =
> - pix_clk_params->requested_pix_clk;
> - pll_settings->adjusted_pix_clk =
> - pix_clk_params->requested_pix_clk;
> + pll_settings->actual_pix_clk_100hz =
> + pix_clk_params->requested_pix_clk_100hz;
> + pll_settings->adjusted_pix_clk_100hz =
> + pix_clk_params->requested_pix_clk_100hz;
>
> if (dc_is_dp_signal(pix_clk_params->signal_type))
> - pll_settings->adjusted_pix_clk = 100000;
> + pll_settings->adjusted_pix_clk_100hz = 1000000;
> }
>
> /* Calculate Dividers */
> @@ -533,28 +533,28 @@ static void dce112_get_pix_clk_dividers_helper (
> struct pll_settings *pll_settings,
> struct pixel_clk_params *pix_clk_params)
> {
> - uint32_t actualPixelClockInKHz;
> + uint32_t actual_pixel_clock_100hz;
>
> - actualPixelClockInKHz = pix_clk_params->requested_pix_clk;
> + actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
> /* Calculate Dividers */
> if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
> switch (pix_clk_params->color_depth) {
> case COLOR_DEPTH_101010:
> - actualPixelClockInKHz = (actualPixelClockInKHz * 5) >> 2;
> + actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
> break;
> case COLOR_DEPTH_121212:
> - actualPixelClockInKHz = (actualPixelClockInKHz * 6) >> 2;
> + actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
> break;
> case COLOR_DEPTH_161616:
> - actualPixelClockInKHz = actualPixelClockInKHz * 2;
> + actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
> break;
> default:
> break;
> }
> }
> - pll_settings->actual_pix_clk = actualPixelClockInKHz;
> - pll_settings->adjusted_pix_clk = actualPixelClockInKHz;
> - pll_settings->calculated_pix_clk = pix_clk_params->requested_pix_clk;
> + pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
> + pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
> + pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
> }
>
> static uint32_t dce110_get_pix_clk_dividers(
> @@ -567,7 +567,7 @@ static uint32_t dce110_get_pix_clk_dividers(
> DC_LOGGER_INIT();
>
> if (pix_clk_params == NULL || pll_settings == NULL
> - || pix_clk_params->requested_pix_clk == 0) {
> + || pix_clk_params->requested_pix_clk_100hz == 0) {
> DC_LOG_ERROR(
> "%s: Invalid parameters!!\n", __func__);
> return pll_calc_error;
> @@ -577,10 +577,10 @@ static uint32_t dce110_get_pix_clk_dividers(
>
> if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
> cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
> - pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
> - pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
> - pll_settings->actual_pix_clk =
> - pix_clk_params->requested_pix_clk;
> + pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
> + pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
> + pll_settings->actual_pix_clk_100hz =
> + pix_clk_params->requested_pix_clk_100hz;
> return 0;
> }
>
> @@ -599,7 +599,7 @@ static uint32_t dce112_get_pix_clk_dividers(
> DC_LOGGER_INIT();
>
> if (pix_clk_params == NULL || pll_settings == NULL
> - || pix_clk_params->requested_pix_clk == 0) {
> + || pix_clk_params->requested_pix_clk_100hz == 0) {
> DC_LOG_ERROR(
> "%s: Invalid parameters!!\n", __func__);
> return -1;
> @@ -609,10 +609,10 @@ static uint32_t dce112_get_pix_clk_dividers(
>
> if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
> cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
> - pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
> - pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
> - pll_settings->actual_pix_clk =
> - pix_clk_params->requested_pix_clk;
> + pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
> + pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
> + pll_settings->actual_pix_clk_100hz =
> + pix_clk_params->requested_pix_clk_100hz;
> return -1;
> }
>
> @@ -714,7 +714,7 @@ static bool enable_spread_spectrum(
> ss_data = get_ss_data_entry(
> clk_src,
> signal,
> - pll_settings->calculated_pix_clk);
> + pll_settings->calculated_pix_clk_100hz / 10);
>
> /* Pixel clock PLL has been programmed to generate desired pixel clock,
> * now enable SS on pixel clock */
> @@ -853,7 +853,7 @@ static bool dce110_program_pix_clk(
> /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
> bp_pc_params.controller_id = pix_clk_params->controller_id;
> bp_pc_params.pll_id = clock_source->id;
> - bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
> + bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
> bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
> bp_pc_params.signal_type = pix_clk_params->signal_type;
>
> @@ -903,12 +903,12 @@ static bool dce112_program_pix_clk(
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
> unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
> - unsigned dp_dto_ref_kHz = 700000;
> - unsigned clock_kHz = pll_settings->actual_pix_clk;
> + unsigned dp_dto_ref_100hz = 7000000;
> + unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
>
> /* Set DTO values: phase = target clock, modulo = reference clock */
> - REG_WRITE(PHASE[inst], clock_kHz);
> - REG_WRITE(MODULO[inst], dp_dto_ref_kHz);
> + REG_WRITE(PHASE[inst], clock_100hz);
> + REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
>
> /* Enable DTO */
> REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
> @@ -927,7 +927,7 @@ static bool dce112_program_pix_clk(
> /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
> bp_pc_params.controller_id = pix_clk_params->controller_id;
> bp_pc_params.pll_id = clock_source->id;
> - bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
> + bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
> bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
> bp_pc_params.signal_type = pix_clk_params->signal_type;
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> index 1d794c6..314c04a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> @@ -599,12 +599,12 @@ bool dce110_link_encoder_validate_dvi_output(
> if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
> connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
> signal != SIGNAL_TYPE_HDMI_TYPE_A &&
> - crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
> + crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
> return false;
> - if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
> + if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
> return false;
>
> - if (crtc_timing->pix_clk_khz > max_pixel_clock)
> + if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
> return false;
>
> /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
> index cce0d18..4bd7c5d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
> @@ -662,7 +662,7 @@ static void dce110_stream_encoder_dvi_set_stream_attribute(
> cntl.signal = is_dual_link ?
> SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
> cntl.enable_dp_audio = false;
> - cntl.pixel_clock = crtc_timing->pix_clk_khz;
> + cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
> cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
>
> if (enc110->base.bp->funcs->encoder_control(
> @@ -686,7 +686,7 @@ static void dce110_stream_encoder_lvds_set_stream_attribute(
> cntl.engine_id = enc110->base.id;
> cntl.signal = SIGNAL_TYPE_LVDS;
> cntl.enable_dp_audio = false;
> - cntl.pixel_clock = crtc_timing->pix_clk_khz;
> + cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
> cntl.lanes_number = LANE_COUNT_FOUR;
>
> if (enc110->base.bp->funcs->encoder_control(
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> index e947cc5..8e961e6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> @@ -1074,7 +1074,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
>
> /* only 3 items below are used by unblank */
> params.pixel_clk_khz =
> - pipe_ctx->stream->timing.pix_clk_khz;
> + pipe_ctx->stream->timing.pix_clk_100hz / 10;
> params.link_settings.link_rate = link_settings->link_rate;
>
> if (dc_is_dp_signal(pipe_ctx->stream->signal))
> @@ -1160,27 +1160,27 @@ static void build_audio_output(
> stream->timing.flags.INTERLACE;
>
> audio_output->crtc_info.refresh_rate =
> - (stream->timing.pix_clk_khz*1000)/
> + (stream->timing.pix_clk_100hz*10000)/
> (stream->timing.h_total*stream->timing.v_total);
>
> audio_output->crtc_info.color_depth =
> stream->timing.display_color_depth;
>
> audio_output->crtc_info.requested_pixel_clock =
> - pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
> + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
>
> audio_output->crtc_info.calculated_pixel_clock =
> - pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
> + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
>
> /*for HDMI, audio ACR is with deep color ratio factor*/
> if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
> audio_output->crtc_info.requested_pixel_clock ==
> - stream->timing.pix_clk_khz) {
> + (stream->timing.pix_clk_100hz / 10)) {
> if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
> audio_output->crtc_info.requested_pixel_clock =
> audio_output->crtc_info.requested_pixel_clock/2;
> audio_output->crtc_info.calculated_pixel_clock =
> - pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
> + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20;
>
> }
> }
> @@ -1621,8 +1621,8 @@ static uint32_t compute_pstate_blackout_duration(
> pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
>
> total_dest_line_time_ns = 1000000UL *
> - stream->timing.h_total /
> - stream->timing.pix_clk_khz +
> + (stream->timing.h_total * 10) /
> + stream->timing.pix_clk_100hz +
> pstate_blackout_duration_ns;
>
> return total_dest_line_time_ns;
> @@ -2567,7 +2567,7 @@ static void dce110_apply_ctx_for_surface(
> pipe_ctx->plane_res.mi,
> pipe_ctx->stream->timing.h_total,
> pipe_ctx->stream->timing.v_total,
> - pipe_ctx->stream->timing.pix_clk_khz,
> + pipe_ctx->stream->timing.pix_clk_100hz / 10,
> context->stream_count);
>
> dce110_program_front_end_for_pipe(dc, pipe_ctx);
> @@ -2622,7 +2622,7 @@ void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
> struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
> struct mem_input *mi = pipe_ctx->plane_res.mi;
> struct dc_cursor_mi_param param = {
> - .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
> + .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
> .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
> .viewport = pipe_ctx->plane_res.scl_data.viewport,
> .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> index 3c989b8..3c27c31 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
> @@ -779,7 +779,7 @@ static void get_pixel_clock_parameters(
> * the pixel clock normalization for hdmi up to here instead of doing it
> * in pll_adjust_pix_clk
> */
> - pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
> + pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
> pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
> pixel_clk_params->signal_type = pipe_ctx->stream->signal;
> pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
> @@ -797,10 +797,10 @@ static void get_pixel_clock_parameters(
> pixel_clk_params->color_depth = COLOR_DEPTH_888;
> }
> if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
> - pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2;
> + pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2;
> }
> if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
> - pixel_clk_params->requested_pix_clk *= 2;
> + pixel_clk_params->requested_pix_clk_100hz *= 2;
>
> }
>
> @@ -874,7 +874,7 @@ static bool dce110_validate_bandwidth(
> __func__,
> context->streams[0]->timing.h_addressable,
> context->streams[0]->timing.v_addressable,
> - context->streams[0]->timing.pix_clk_khz);
> + context->streams[0]->timing.pix_clk_100hz / 10);
>
> if (memcmp(&dc->current_state->bw.dce,
> &context->bw.dce, sizeof(context->bw.dce))) {
> @@ -1055,7 +1055,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
> pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
> stream->timing.h_total,
> stream->timing.v_total,
> - stream->timing.pix_clk_khz,
> + stream->timing.pix_clk_100hz / 10,
> context->stream_count);
>
> color_space_to_black_color(dc,
> diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
> index 3ba4712..5c629ae 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
> @@ -84,17 +84,17 @@ static const struct dce110_timing_generator_offsets reg_offsets[] = {
> #define DCP_REG(reg) (reg + tg110->offsets.dcp)
> #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
>
> -static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
> +static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
> {
> uint64_t pix_dur;
> uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
> + DCE110TG_FROM_TG(tg)->offsets.dmif;
> uint32_t value = dm_read_reg(tg->ctx, addr);
>
> - if (pix_clk_khz == 0)
> + if (pix_clk_100hz == 0)
> return;
>
> - pix_dur = 1000000000 / pix_clk_khz;
> + pix_dur = 10000000000ull / pix_clk_100hz;
>
> set_reg_field_value(
> value,
> @@ -110,7 +110,7 @@ static void program_timing(struct timing_generator *tg,
> bool use_vbios)
> {
> if (!use_vbios)
> - program_pix_dur(tg, timing->pix_clk_khz);
> + program_pix_dur(tg, timing->pix_clk_100hz);
>
> dce110_tg_program_timing(tg, timing, use_vbios);
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 613293d..05c6152 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -2655,7 +2655,7 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
> struct hubp *hubp = pipe_ctx->plane_res.hubp;
> struct dpp *dpp = pipe_ctx->plane_res.dpp;
> struct dc_cursor_mi_param param = {
> - .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
> + .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
> .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
> .viewport = pipe_ctx->plane_res.scl_data.viewport,
> .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> index ae4fd5e..19d15ec 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> @@ -429,7 +429,7 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int
> int pix_clk = 0;
>
> optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
> - pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk;
> + pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
>
> //only print if OTG master is enabled
> if (s.otg_enabled & 1) {
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> index aefe897..af0bcff 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> @@ -543,12 +543,12 @@ bool dcn10_link_encoder_validate_dvi_output(
> if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
> connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
> signal != SIGNAL_TYPE_HDMI_TYPE_A &&
> - crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
> + crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
> return false;
> - if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
> + if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
> return false;
>
> - if (crtc_timing->pix_clk_khz > max_pixel_clock)
> + if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
> return false;
>
> /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
> @@ -571,7 +571,7 @@ bool dcn10_link_encoder_validate_dvi_output(
> static bool dcn10_link_encoder_validate_hdmi_output(
> const struct dcn10_link_encoder *enc10,
> const struct dc_crtc_timing *crtc_timing,
> - int adjusted_pix_clk_khz)
> + int adjusted_pix_clk_100hz)
> {
> enum dc_color_depth max_deep_color =
> enc10->base.features.max_hdmi_deep_color;
> @@ -581,11 +581,11 @@ static bool dcn10_link_encoder_validate_hdmi_output(
>
> if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
> return false;
> - if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
> + if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
> return false;
>
> - if ((adjusted_pix_clk_khz == 0) ||
> - (adjusted_pix_clk_khz > enc10->base.features.max_hdmi_pixel_clock))
> + if ((adjusted_pix_clk_100hz == 0) ||
> + (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
> return false;
>
> /* DCE11 HW does not support 420 */
> @@ -594,7 +594,7 @@ static bool dcn10_link_encoder_validate_hdmi_output(
> return false;
>
> if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
> - adjusted_pix_clk_khz >= 300000)
> + adjusted_pix_clk_100hz >= 3000000)
> return false;
> if (enc10->base.ctx->dc->debug.hdmi20_disable &&
> crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> @@ -746,7 +746,7 @@ bool dcn10_link_encoder_validate_output_with_stream(
> is_valid = dcn10_link_encoder_validate_hdmi_output(
> enc10,
> &stream->timing,
> - stream->phy_pix_clk);
> + stream->phy_pix_clk * 10);
> break;
> case SIGNAL_TYPE_DISPLAY_PORT:
> case SIGNAL_TYPE_DISPLAY_PORT_MST:
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
> index 57d00d6..eb019d4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
> @@ -126,7 +126,7 @@ void optc1_program_vline_interrupt(
> struct optc *optc1 = DCN10TG_FROM_TG(optc);
>
> unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
> - unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
> + unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_100hz + 999), 1000);
> uint32_t req_delta_lines = (uint32_t) div64_u64(
> (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
> dc_crtc_timing->h_total);
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> index 83447cd..add84f9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> @@ -974,7 +974,7 @@ static void get_pixel_clock_parameters(
> struct pixel_clk_params *pixel_clk_params)
> {
> const struct dc_stream_state *stream = pipe_ctx->stream;
> - pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
> + pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
> pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
> pixel_clk_params->signal_type = pipe_ctx->stream->signal;
> pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
> @@ -991,9 +991,9 @@ static void get_pixel_clock_parameters(
> pixel_clk_params->color_depth = COLOR_DEPTH_888;
>
> if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
> - pixel_clk_params->requested_pix_clk /= 2;
> + pixel_clk_params->requested_pix_clk_100hz /= 2;
> if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
> - pixel_clk_params->requested_pix_clk *= 2;
> + pixel_clk_params->requested_pix_clk_100hz *= 2;
>
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> index b8b5525..0b0e06f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> @@ -594,7 +594,7 @@ void enc1_stream_encoder_dvi_set_stream_attribute(
> cntl.signal = is_dual_link ?
> SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
> cntl.enable_dp_audio = false;
> - cntl.pixel_clock = crtc_timing->pix_clk_khz;
> + cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
> cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
>
> if (enc1->base.bp->funcs->encoder_control(
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
> index 47ef904..43d1fbd 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
> @@ -78,7 +78,7 @@ struct csdp_ref_clk_ds_params {
> };
>
> struct pixel_clk_params {
> - uint32_t requested_pix_clk; /* in KHz */
> + uint32_t requested_pix_clk_100hz;
> /*> Requested Pixel Clock
> * (based on Video Timing standard used for requested mode)*/
> uint32_t requested_sym_clk; /* in KHz */
> @@ -104,9 +104,9 @@ struct pixel_clk_params {
> * with actually calculated Clock and reference Crystal frequency
> */
> struct pll_settings {
> - uint32_t actual_pix_clk;
> - uint32_t adjusted_pix_clk;
> - uint32_t calculated_pix_clk;
> + uint32_t actual_pix_clk_100hz;
> + uint32_t adjusted_pix_clk_100hz;
> + uint32_t calculated_pix_clk_100hz;
> uint32_t vco_freq;
> uint32_t reference_freq;
> uint32_t reference_divider;
> diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
> index f8dbfa5..b14b3c2 100644
> --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
> +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
> @@ -210,8 +210,8 @@ struct bp_pixel_clock_parameters {
> /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
> enum signal_type signal_type;
> /* Adjusted Pixel Clock (after VBIOS exec table)
> - * that becomes Target Pixel Clock (KHz) */
> - uint32_t target_pixel_clock;
> + * that becomes Target Pixel Clock (100 Hz units) */
> + uint32_t target_pixel_clock_100hz;
> /* Calculated Reference divider of Display PLL */
> uint32_t reference_divider;
> /* Calculated Feedback divider of Display PLL */
> diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> index 1544ed3..d967ac0 100644
> --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> @@ -108,8 +108,8 @@ static unsigned int calc_duration_in_us_from_v_total(
> {
> unsigned int duration_in_us =
> (unsigned int)(div64_u64(((unsigned long long)(v_total)
> - * 1000) * stream->timing.h_total,
> - stream->timing.pix_clk_khz));
> + * 10000) * stream->timing.h_total,
> + stream->timing.pix_clk_100hz));
>
> return duration_in_us;
> }
> @@ -126,7 +126,7 @@ static unsigned int calc_v_total_from_refresh(
> refresh_in_uhz)));
>
> v_total = div64_u64(div64_u64(((unsigned long long)(
> - frame_duration_in_ns) * stream->timing.pix_clk_khz),
> + frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
> stream->timing.h_total), 1000000);
>
> /* v_total cannot be less than nominal */
> @@ -152,7 +152,7 @@ static unsigned int calc_v_total_from_duration(
> duration_in_us = vrr->max_duration_in_us;
>
> v_total = div64_u64(div64_u64(((unsigned long long)(
> - duration_in_us) * stream->timing.pix_clk_khz),
> + duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
> stream->timing.h_total), 1000);
>
> /* v_total cannot be less than nominal */
> @@ -227,7 +227,7 @@ static void update_v_total_for_static_ramp(
> }
>
> v_total = div64_u64(div64_u64(((unsigned long long)(
> - current_duration_in_us) * stream->timing.pix_clk_khz),
> + current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
> stream->timing.h_total), 1000);
>
> in_out_vrr->adjust.v_total_min = v_total;
> @@ -972,7 +972,7 @@ unsigned long long mod_freesync_calc_nominal_field_rate(
> unsigned long long nominal_field_rate_in_uhz = 0;
>
> /* Calculate nominal field rate for stream */
> - nominal_field_rate_in_uhz = stream->timing.pix_clk_khz;
> + nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz / 10;
> nominal_field_rate_in_uhz *= 1000ULL * 1000ULL * 1000ULL;
> nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
> stream->timing.h_total);
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