[PATCH 5/6] drm/amdgpu/vcn:Wait for all vcn rings finish before switching dpg mode

[Zhu, James]

For robustness, it is safe to wait for all vcn rings finish
before switching dpg mode.

Signed-off-by: James Zhu <James.Zhu at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index dde7bcd..564ed94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -219,6 +219,23 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
 	uint32_t reg_data = 0;
 	uint32_t reg_data2 = 0;
 	struct amdgpu_ring *ring;
+	uint32_t tmp, i;
+
+	if ((adev->vcn.pause_state.fw_based != new_state->fw_based) ||
+		(adev->vcn.pause_state.jpeg != new_state->jpeg)) {
+		/* wait for read ptr to be equal to write ptr */
+		tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
+		SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+
+		tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
+		SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
+
+		tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+		SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+
+		tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
+		SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+	}
 
 	/* pause/unpause if state is changed */
 	if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
-- 
2.7.4