[PATCH 06/10] drm/amd/pp: Implement set_power_profile_mode on smu7

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> User can set smu7 dpm pamameters through sysfs
>
> Depending on the workloads,
> user can echo "0/1/2/3/4">pp_power_profile_mode
> to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE
> mode.
>
> echo "5 * * * * * * * *">pp_power_profile_mode
> to config custom mode.
> "5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST
> SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST
> MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL"
>
> if the parameter enable_sclk/enable_mclk is true,
> driver will update the following parameters to dpm table.
> if false, ignore the following parameters.
>
> Change-Id: I8b5fc6fb2e20e6cd50b4184458452ac22c562469
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 52 ++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 8cf95d9..08e9e44 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5019,6 +5019,57 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
>         return size;
>  }
>
> +static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
> +{
> +       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +       struct profile_mode_setting tmp;
> +
> +       hwmgr->power_profile_mode = input[size];
> +
> +       switch (hwmgr->power_profile_mode) {
> +       case PP_SMC_POWER_PROFILE_CUSTOM:
> +               if (size < 8)
> +                       return -EINVAL;
> +
> +               data->custom_profile_setting.bupdate_sclk = input[0];
> +               data->custom_profile_setting.sclk_up_hyst = input[1];
> +               data->custom_profile_setting.sclk_down_hyst = input[2];
> +               data->custom_profile_setting.sclk_activity =  input[3];
> +               data->custom_profile_setting.bupdate_mclk = input[4];
> +               data->custom_profile_setting.mclk_up_hyst = input[5];
> +               data->custom_profile_setting.mclk_down_hyst = input[6];
> +               data->custom_profile_setting.mclk_activity =  input[7];
> +               if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting))
> +                       memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting));
> +               break;
> +       case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
> +       case PP_SMC_POWER_PROFILE_POWERSAVING:
> +       case PP_SMC_POWER_PROFILE_VIDEO:
> +       case PP_SMC_POWER_PROFILE_VR:
> +       case PP_SMC_POWER_PROFILE_COMPUTE:
> +               memcpy(&tmp, &smu7_profiling[hwmgr->power_profile_mode], sizeof(struct profile_mode_setting));
> +               if (!smum_update_dpm_settings(hwmgr, &tmp)) {

Won't the lack of an update_dpm_settings mean we can't manually select
power profiles on non-polaris asics?  Didn't your previous patches
allow this on non-polaris parts?

Alex

> +                       if (tmp.bupdate_sclk) {
> +                               data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
> +                               data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
> +                               data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
> +                               data->current_profile_setting.sclk_activity = tmp.sclk_activity;
> +                       }
> +                       if (tmp.bupdate_mclk) {
> +                               data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
> +                               data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
> +                               data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
> +                               data->current_profile_setting.mclk_activity = tmp.mclk_activity;
> +                       }
> +               }
> +               break;
> +       default:
> +               return -EINVAL;
> +       }
> +
> +       return 0;
> +}
> +
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>         .backend_init = &smu7_hwmgr_backend_init,
>         .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -5075,6 +5126,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
>         .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
>         .set_power_limit = smu7_set_power_limit,
>         .get_power_profile_mode = smu7_get_power_profile_mode,
> +       .set_power_profile_mode = smu7_set_power_profile_mode,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx