[PATCH 5/5] drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching

[Eric Huang]

The series: Reviewed-by: Eric Huang <JinhuiEric.Huang at amd.com>


On 2018-02-13 02:46 PM, Alex Deucher wrote:
> The logic has moved to cgs.  mclk switching with DC at higher refresh
> rates should work.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> Cc: Harry Wentland <harry.wentland. at amd.com>
> ---
>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 84600ff6f4de..0202841ae639 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2909,8 +2909,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
>   	else
>   		disable_mclk_switching = ((1 < info.display_count) ||
>   					  disable_mclk_switching_for_frame_lock ||
> -					  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
> -					  (mode_info.refresh_rate > 120));
> +					  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
>   
>   	sclk = smu7_ps->performance_levels[0].engine_clock;
>   	mclk = smu7_ps->performance_levels[0].memory_clock;