[PATCH 4/4] drm/amd/pp: Disable power containment on Fiji with compute workload

[Rex Zhu]

disable power containment on Fiji in order to get better compute performance
it is a temporary workaround. we can adjust power/current limit
to satify compute request.

Change-Id: I26389a3ff84e1f74e599541b44c0e62ce38a7345
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a31d1a8..e725455 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2782,6 +2782,8 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
 
 			smu7_set_power_profile_mode(hwmgr, &mode, 0);
 		}
+		if (hwmgr->chip_id == CHIP_FIJI)
+			smu7_enable_power_containment(hwmgr);
 
 		ret = smu7_unforce_dpm_levels(hwmgr);
 		break;
@@ -5032,6 +5034,9 @@ static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
 	uint32_t tmp, level;
 
 	if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
+		if (hwmgr->chip_id == CHIP_FIJI)
+			smu7_disable_power_containment(hwmgr);
+
 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
 			level = 0;
 			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
@@ -5042,6 +5047,8 @@ static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
 		}
 	} else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
 		smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
+		if (hwmgr->chip_id == CHIP_FIJI)
+			smu7_enable_power_containment(hwmgr);
 	}
 }
 
-- 
1.9.1