[PATCH 1/2] drm/amdgpu: adjust HDP write queue flushing for tlb invalidation

[Christian König]

Am 05.01.2018 um 16:58 schrieb Alex Deucher:
> Separate tlb invalidation and hdp flushing and move the HDP
> flush to the caller.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com> for the series.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 2 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 2 ++
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    | 2 --
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    | 3 ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    | 3 ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    | 3 ---
>   6 files changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index 0a4f34afaaaa..d0617f1c252f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -247,6 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
>   		}
>   	}
>   	mb();
> +	amdgpu_asic_flush_hdp(adev);
>   	amdgpu_gart_flush_gpu_tlb(adev, 0);
>   	return 0;
>   }
> @@ -329,6 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
>   		return r;
>   
>   	mb();
> +	amdgpu_asic_flush_hdp(adev);
>   	amdgpu_gart_flush_gpu_tlb(adev, 0);
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index cd1752b6afa9..2d5c1aa7322a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -856,6 +856,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
>   	if (vm->use_cpu_for_update) {
>   		/* Flush HDP */
>   		mb();
> +		amdgpu_asic_flush_hdp(adev);
>   		amdgpu_gart_flush_gpu_tlb(adev, 0);
>   	} else if (params.ib->length_dw == 0) {
>   		amdgpu_job_free(job);
> @@ -1453,6 +1454,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
>   	if (vm->use_cpu_for_update) {
>   		/* Flush HDP */
>   		mb();
> +		amdgpu_asic_flush_hdp(adev);
>   		amdgpu_gart_flush_gpu_tlb(adev, 0);
>   	}
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 8e28270d1ea9..da708356eefc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -359,8 +359,6 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
>   static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
>   					uint32_t vmid)
>   {
> -	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> -
>   	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 86e9d682c59e..b73599912b42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -431,9 +431,6 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
>   static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
>   					uint32_t vmid)
>   {
> -	/* flush hdp cache */
> -	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> -
>   	/* bits 0-15 are the VM contexts0-15 */
>   	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 9a813d834f1a..287228315b76 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -606,9 +606,6 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
>   static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
>   					uint32_t vmid)
>   {
> -	/* flush hdp cache */
> -	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
> -
>   	/* bits 0-15 are the VM contexts0-15 */
>   	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index eb8b1bb66389..7ec54c23c07d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -329,9 +329,6 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
>   	const unsigned eng = 17;
>   	unsigned i, j;
>   
> -	/* flush hdp cache */
> -	adev->nbio_funcs->hdp_flush(adev);
> -
>   	spin_lock(&adev->mc.invalidate_lock);
>   
>   	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {