[PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory

[Zhang, Jerry (Junwei)]

On 01/10/2018 04:57 PM, Christian König wrote:
> Am 10.01.2018 um 09:18 schrieb Junwei Zhang:
>> Signed-off-by: Junwei Zhang <Jerry.Zhang at amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++++---
>>   1 file changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index ae976e3..5f2ae77 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -1069,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
>>       adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
>>       adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
>>       adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
>> -    adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
>> +    adev->gfx.ngg.gds_reserve_addr += SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE);
>
> Both the old and the new code looks strongly incorrect to me.
>
> SOC15_REG_OFFSET gives you the register offset, not the content of the register.
>
> So adding two register offsets or doesn't seem to make any sense at all.

Thanks to point it out.
It's typo from the very beginning.
Going to correct it with RREG32_SOC15().

Jerry

>
> Regards,
> Christian.
>
>>       /* Primitive Buffer */
>>       r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
>> @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
>>       amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
>>       amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
>> +                PACKET3_DMA_DATA_DST_SEL(0) |
>>                   PACKET3_DMA_DATA_SRC_SEL(2)));
>>       amdgpu_ring_write(ring, 0);
>>       amdgpu_ring_write(ring, 0);
>>       amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
>>       amdgpu_ring_write(ring, 0);
>> -    amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
>> -
>> +    amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS |
>> +                PACKET3_DMA_DATA_CMD_RAW_WAIT |
>> +                adev->gfx.ngg.gds_reserve_size);
>>       gfx_v9_0_write_data_to_reg(ring, 0, false,
>>                      SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
>