Additional register waits in MM engines on Vega10

Leo Liu leo.liu at amd.com
Mon Jan 15 14:11:30 UTC 2018



On 01/15/2018 07:21 AM, Christian König wrote:
> Hi guys,
>
> The *_vm_flush functions on Vega10 insert an extra register wait before writing to the request register.
>
> That doesn't looks like it makes any sense to me and I think it is just a leftover from bringup.

The sequences is based on internal MM doc for UVD/VCE vm flush. Not sure 
how firmware handling all the writes, if the write sequence happens 
exactly in order, the first wait should be useless.

>
> Now it's in the way of cleaning up the *_vm_flush functions into something common. So can we remove it?

Let me confirm with them first.

Regards,
Leo

>
> Thanks,
> Christian.
>



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