[PATCH 5/5] drm/amd/pp: Implement get_power_profile_mode on smu7
Zhu, Rex
Rex.Zhu at amd.com
Wed Jan 24 00:29:41 UTC 2018
>>Is there a reason why you added a CURRENT field? This should be consistent with vega10. Also, please add an AUTO profile for both asics to >>support dynamic driver controlled profile selection so the API is in place even if it's not hooked up yet.
Yes, On SMU7, just need to adjust sclk parameters for COMPUTE mode, adjust mclk parameters for VIDEO mode.
so on those two mode, the profiling parameters are not unique.
When cat pp_power_profile_mode, there are some "*" in the output.
as
VIDEO: * * * 10 16 31
so add current_mode to notify user current parameters.
Best Regards
Rex
________________________________
From: Deucher, Alexander
Sent: Tuesday, January 23, 2018 11:15 PM
To: Zhu, Rex; amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH 5/5] drm/amd/pp: Implement get_power_profile_mode on smu7
Patches 1-4:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
patch 5:
Is there a reason why you added a CURRENT field? This should be consistent with vega10. Also, please add an AUTO profile for both asics to support dynamic driver controlled profile selection so the API is in place even if it's not hooked up yet.
Alex
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Tuesday, January 23, 2018 5:05:02 AM
To: amd-gfx at lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 5/5] drm/amd/pp: Implement get_power_profile_mode on smu7
User can get smu7 profile pamameters through sysfs
cat pp_power_profile_mode
NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
0 3D_FULL_SCREEN: 0 100 30 0 100 10
1 POWER_SAVING: 10 0 30 * * *
2 VIDEO: * * * 10 16 31
3 VR: 0 11 50 0 100 10
4 COMPUTE: 0 5 30 * * *
5 CUSTOM: 0 0 0 0 0 0
* CURRENT: 0 100 30 0 100 10
Change-Id: I10e02f9e5fcd8e2b62c0cad620d9635336ea01dd
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 94 ++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 1 +
2 files changed, 95 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f6236f9..7d68e23 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -81,6 +81,21 @@
#define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10)
+static const struct profile_mode_setting smu7_profiling[5] =
+ {{1, 0, 100, 30, 1, 0, 100, 10},
+ {1, 10, 0, 30, 0, 0, 0, 0},
+ {0, 0, 0, 0, 1, 10, 16, 31},
+ {1, 0, 11, 50, 1, 0, 100, 10},
+ {1, 0, 5, 30, 0, 0, 0, 0},
+ };
+
+static const struct profile_mode_setting polaris11_profiling[5] =
+ {{1, 0, 100, 30, 1, 0, 100, 10},
+ {1, 10, 0, 30, 0, 0, 0, 0},
+ {0, 0, 0, 0, 1, 10, 16, 62},
+ {1, 0, 11, 50, 1, 0, 100, 10},
+ {1, 0, 5, 30, 0, 0, 0, 0},
+ };
/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
enum DPM_EVENT_SRC {
@@ -4934,6 +4949,83 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
return 0;
}
+static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t i, size = 0;
+ uint32_t len;
+
+ static const char *profile_name[6] = {"3D_FULL_SCREEN",
+ "POWER_SAVING",
+ "VIDEO",
+ "VR",
+ "COMPUTE",
+ "CUSTOM"};
+
+ static const char *title[8] = {"NUM",
+ "MODE_NAME",
+ "SCLK_UP_HYST",
+ "SCLK_DOWN_HYST",
+ "SCLK_ACTIVE_LEVEL",
+ "MCLK_UP_HYST",
+ "MCLK_DOWN_HYST",
+ "MCLK_ACTIVE_LEVEL"};
+
+ if (!buf)
+ return -EINVAL;
+
+ size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
+ title[0], title[1], title[2], title[3],
+ title[4], title[5], title[6], title[7]);
+
+ len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
+
+ for (i = 0; i < len; i++) {
+ if (smu7_profiling[i].bupdate_sclk)
+ size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
+ i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
+ smu7_profiling[i].sclk_down_hyst,
+ smu7_profiling[i].sclk_activity);
+ else
+ size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
+ i, profile_name[i], "*", "*", "*");
+
+ if (smu7_profiling[i].bupdate_mclk)
+ size += sprintf(buf + size, "%16d %16d %16d\n",
+ smu7_profiling[i].mclk_up_hyst,
+ smu7_profiling[i].mclk_down_hyst,
+ smu7_profiling[i].mclk_activity);
+ else
+ size += sprintf(buf + size, "%16s %16s %16s\n",
+ "*", "*", "*");
+ }
+
+ size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
+ i, profile_name[i],
+ data->custom_profile_setting.sclk_up_hyst,
+ data->custom_profile_setting.sclk_down_hyst,
+ data->custom_profile_setting.sclk_activity,
+ data->custom_profile_setting.mclk_up_hyst,
+ data->custom_profile_setting.mclk_down_hyst,
+ data->custom_profile_setting.mclk_activity);
+
+ size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
+ "*", "CURRENT",
+ data->current_profile_setting.sclk_up_hyst,
+ data->current_profile_setting.sclk_down_hyst,
+ data->current_profile_setting.sclk_activity,
+ data->current_profile_setting.mclk_up_hyst,
+ data->current_profile_setting.mclk_down_hyst,
+ data->current_profile_setting.mclk_activity);
+
+ return size;
+}
+
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
+{
+ /* To Do */
+ return 0;
+}
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init,
@@ -4990,6 +5082,8 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
.get_max_high_clocks = smu7_get_max_high_clocks,
.get_thermal_temperature_range = smu7_get_thermal_temperature_range,
.odn_edit_dpm_table = smu7_odn_edit_dpm_table,
+ .get_power_profile_mode = smu7_get_power_profile_mode,
+ .set_power_profile_mode = smu7_set_power_profile_mode,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index 3bcfc61..51aa4b3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -327,6 +327,7 @@ struct smu7_hwmgr {
uint32_t vr_config;
struct profile_mode_setting custom_profile_setting;
struct profile_mode_setting current_profile_setting;
+ enum PP_SMC_POWER_PROFILE profile_mode;
};
/* To convert to Q8.8 format for firmware */
--
1.9.1
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