[PATCH] drm/amdgpu: fix DW estimation on VI

[Alex Deucher]

On Tue, Jan 30, 2018 at 10:03 AM, Christian König
<ckoenig.leichtzumerken at gmail.com> wrote:
> Forgot to update that during recent changes.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  | 4 +++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 83dde3b4c3ae..5680ced69359 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1628,7 +1628,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
>                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
>                 3 + /* hdp invalidate */
>                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
> -               12 + /* sdma_v3_0_ring_emit_vm_flush */
> +               VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
>                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
>         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
>         .emit_ib = sdma_v3_0_ring_emit_ib,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index e7546d5b301c..0f192ab71205 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1530,6 +1530,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
>         .set_wptr = uvd_v6_0_ring_set_wptr,
>         .parse_cs = amdgpu_uvd_ring_parse_cs,
>         .emit_frame_size =
> +               6 + 6 + /* hdp flush / invalidate */
>                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
>                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
>         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
> @@ -1541,6 +1542,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
>         .pad_ib = amdgpu_ring_generic_pad_ib,
>         .begin_use = amdgpu_uvd_ring_begin_use,
>         .end_use = amdgpu_uvd_ring_end_use,
> +       .emit_wreg = uvd_v6_0_ring_emit_wreg,
>  };
>
>  static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
> @@ -1554,7 +1556,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
>         .emit_frame_size =
>                 6 + 6 + /* hdp flush / invalidate */
>                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
> -               20 + /* uvd_v6_0_ring_emit_vm_flush */
> +               VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
>                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
>         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
>         .emit_ib = uvd_v6_0_ring_emit_ib,
> --
> 2.14.1
>
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