[PATCH 2/5] drm/amdgpu: update amd_pcie.h to include gen4 speeds

[Alex Deucher]

On Mon, Jun 25, 2018 at 5:06 PM, Alex Deucher <alexdeucher at gmail.com> wrote:
> Internal header used by the driver to specify pcie gen
> speeds of the asic and chipset.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Anyone care to review patches 2,3,4?

> ---
>  drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
> index 5eb895fd98bf..9cb9ceb4d74d 100644
> --- a/drivers/gpu/drm/amd/include/amd_pcie.h
> +++ b/drivers/gpu/drm/amd/include/amd_pcie.h
> @@ -27,6 +27,7 @@
>  #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
>  #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
>  #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
> +#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4        0x00080000
>  #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
>  #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
>
> @@ -34,6 +35,7 @@
>  #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
>  #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
>  #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
> +#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4   0x00000008
>  #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
>  #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
>
> --
> 2.13.6
>