[PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu

[Alex Deucher]

On Thu, Jul 5, 2018 at 10:00 AM, Rex Zhu <rex.zhu at amd.com> wrote:
> display can get clock info through this function.
> implement this function for vega10 and old asics.
> from vega12, there is no power state management. so need other
> interface to notify display the clock info
>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 24 ++++++++++++++++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ++++++++++++++++++++++
>  3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index 53207e7..b05b153 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -357,7 +357,7 @@ int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *s
>                         PHM_PerformanceLevelDesignation designation)
>  {
>         int result;
> -       PHM_PerformanceLevel performance_level;
> +       PHM_PerformanceLevel performance_level = {0};
>
>         PHM_FUNC_CHECK(hwmgr);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 077b799..8eaaa6b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5006,6 +5006,29 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
>         return 0;
>  }
>
> +static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
> +                               PHM_PerformanceLevelDesignation designation, uint32_t index,
> +                               PHM_PerformanceLevel *level)
> +{
> +       const struct smu7_power_state *ps;
> +       struct smu7_hwmgr *data;
> +       uint32_t i;
> +
> +       if (level == NULL || hwmgr == NULL || state == NULL)
> +               return -EINVAL;
> +
> +       data = hwmgr->backend;
> +       ps = cast_const_phw_smu7_power_state(state);
> +
> +       i = index > ps->performance_level_count - 1 ?
> +                       ps->performance_level_count - 1 : index;
> +
> +       level->coreClock = ps->performance_levels[i].engine_clock;
> +       level->memory_clock = ps->performance_levels[i].memory_clock;
> +
> +       return 0;
> +}
> +
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>         .backend_init = &smu7_hwmgr_backend_init,
>         .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -5062,6 +5085,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
>         .set_power_limit = smu7_set_power_limit,
>         .get_power_profile_mode = smu7_get_power_profile_mode,
>         .set_power_profile_mode = smu7_set_power_profile_mode,
> +       .get_performance_level = smu7_get_performance_level,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index eb37316..5c03df4 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4837,6 +4837,29 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
>         return 0;
>  }
>
> +static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
> +                               PHM_PerformanceLevelDesignation designation, uint32_t index,
> +                               PHM_PerformanceLevel *level)
> +{
> +       const struct vega10_power_state *ps;
> +       struct vega10_hwmgr *data;
> +       uint32_t i;
> +
> +       if (level == NULL || hwmgr == NULL || state == NULL)
> +               return -EINVAL;
> +
> +       data = hwmgr->backend;
> +       ps = cast_const_phw_vega10_power_state(state);
> +
> +       i = index > ps->performance_level_count - 1 ?
> +                       ps->performance_level_count - 1 : index;
> +
> +       level->coreClock = ps->performance_levels[i].gfx_clock;
> +       level->memory_clock = ps->performance_levels[i].mem_clock;
> +
> +       return 0;
> +}
> +
>  static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
>         .backend_init = vega10_hwmgr_backend_init,
>         .backend_fini = vega10_hwmgr_backend_fini,
> @@ -4896,6 +4919,7 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
>         .set_power_profile_mode = vega10_set_power_profile_mode,
>         .set_power_limit = vega10_set_power_limit,
>         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
> +       .get_performance_level = vega10_get_performance_level,
>  };
>
>  int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx