[PATCH] drm/amd/pp: revert "Implement get_performance_level for legacy dgpu"

Harry Wentland harry.wentland at amd.com
Mon Jul 9 18:08:54 UTC 2018


On 2018-07-09 09:24 AM, Christian König wrote:
> This reverts commit 3fdadbfe1edf4168b2515083af5651c95aeb299d.
> 
> It causes crashes on Tonga so revert it for now. Somebody with better knowledge
> of the code needs to take a closer look.
> 
> Signed-off-by: Christian König <christian.koenig at amd.com>

Acked-by: Harry Wentland <harry.wentland at amd.com>

Harry

> ---
>  .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 24 ----------------------
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ----------------------
>  3 files changed, 1 insertion(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index b05b153101c5..53207e76b0f3 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -357,7 +357,7 @@ int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *s
>  			PHM_PerformanceLevelDesignation designation)
>  {
>  	int result;
> -	PHM_PerformanceLevel performance_level = {0};
> +	PHM_PerformanceLevel performance_level;
>  
>  	PHM_FUNC_CHECK(hwmgr);
>  
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 8eaaa6b7973e..077b79938528 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5006,29 +5006,6 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
>  	return 0;
>  }
>  
> -static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
> -				PHM_PerformanceLevelDesignation designation, uint32_t index,
> -				PHM_PerformanceLevel *level)
> -{
> -	const struct smu7_power_state *ps;
> -	struct smu7_hwmgr *data;
> -	uint32_t i;
> -
> -	if (level == NULL || hwmgr == NULL || state == NULL)
> -		return -EINVAL;
> -
> -	data = hwmgr->backend;
> -	ps = cast_const_phw_smu7_power_state(state);
> -
> -	i = index > ps->performance_level_count - 1 ?
> -			ps->performance_level_count - 1 : index;
> -
> -	level->coreClock = ps->performance_levels[i].engine_clock;
> -	level->memory_clock = ps->performance_levels[i].memory_clock;
> -
> -	return 0;
> -}
> -
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>  	.backend_init = &smu7_hwmgr_backend_init,
>  	.backend_fini = &smu7_hwmgr_backend_fini,
> @@ -5085,7 +5062,6 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>  	.set_power_limit = smu7_set_power_limit,
>  	.get_power_profile_mode = smu7_get_power_profile_mode,
>  	.set_power_profile_mode = smu7_set_power_profile_mode,
> -	.get_performance_level = smu7_get_performance_level,
>  };
>  
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 5c03df49c076..eb37316cfbf7 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4837,29 +4837,6 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
>  	return 0;
>  }
>  
> -static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
> -				PHM_PerformanceLevelDesignation designation, uint32_t index,
> -				PHM_PerformanceLevel *level)
> -{
> -	const struct vega10_power_state *ps;
> -	struct vega10_hwmgr *data;
> -	uint32_t i;
> -
> -	if (level == NULL || hwmgr == NULL || state == NULL)
> -		return -EINVAL;
> -
> -	data = hwmgr->backend;
> -	ps = cast_const_phw_vega10_power_state(state);
> -
> -	i = index > ps->performance_level_count - 1 ?
> -			ps->performance_level_count - 1 : index;
> -
> -	level->coreClock = ps->performance_levels[i].gfx_clock;
> -	level->memory_clock = ps->performance_levels[i].mem_clock;
> -
> -	return 0;
> -}
> -
>  static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
>  	.backend_init = vega10_hwmgr_backend_init,
>  	.backend_fini = vega10_hwmgr_backend_fini,
> @@ -4919,7 +4896,6 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
>  	.set_power_profile_mode = vega10_set_power_profile_mode,
>  	.set_power_limit = vega10_set_power_limit,
>  	.odn_edit_dpm_table = vega10_odn_edit_dpm_table,
> -	.get_performance_level = vega10_get_performance_level,
>  };
>  
>  int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
> 


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