[PATCH 06/10] drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE

[Alex Deucher]

On Mon, Jul 9, 2018 at 12:06 AM, Quan, Evan <Evan.Quan at amd.com> wrote:
> Ping..
>
>> -----Original Message-----
>> From: Evan Quan [mailto:evan.quan at amd.com]
>> Sent: Thursday, July 05, 2018 5:10 PM
>> To: amd-gfx at lists.freedesktop.org
>> Cc: Quan, Evan <Evan.Quan at amd.com>
>> Subject: [PATCH 06/10] drm/amdgpu: no touch for the reserved bit of
>> RLC_CGTT_MGCG_OVERRIDE
>>
>> On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved.
>>
>> Change-Id: I9042a8c89db16f220da5a589264937b51870c187
>> Signed-off-by: Evan Quan <evan.quan at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++++++++++----
>>  1 file changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 3a75641a071d..ee537423af11 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3551,8 +3551,11 @@ static void
>> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>>       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
>>               /* 1 - RLC_CGTT_MGCG_OVERRIDE */
>>               def = data = RREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE);
>> -             data &=
>> ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
>> -
>> RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
>> +
>> +             if (adev->asic_type != CHIP_VEGA12)
>> +                     data &=
>> ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>> +
>> +             data &=
>> ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
>>
>> @@ -3582,11 +3585,15 @@ static void
>> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>>       } else {
>>               /* 1 - MGCG_OVERRIDE */
>>               def = data = RREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE);
>> -             data |=
>> (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
>> -
>> RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
>> +
>> +             if (adev->asic_type != CHIP_VEGA12)
>> +                     data |=
>> RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>> +
>> +             data |=
>> (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
>> +
>>               if (def != data)
>>                       WREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE, data);
>>
>> --
>> 2.18.0
>
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