[PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

[Alex Deucher]

On Mon, Jul 9, 2018 at 12:06 AM, Quan, Evan <Evan.Quan at amd.com> wrote:
> Ping..
>
>> -----Original Message-----
>> From: Evan Quan [mailto:evan.quan at amd.com]
>> Sent: Thursday, July 05, 2018 5:10 PM
>> To: amd-gfx at lists.freedesktop.org
>> Cc: Quan, Evan <Evan.Quan at amd.com>
>> Subject: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to
>> wait before request CGCG
>>
>> Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
>> change will help to enable gfxoff feature more frequently.


I assume this is ok for RV gfxoff as well?  if so:
Acked-by: Alex Deucher <alexander.deucher at amd.com>



>>
>> Change-Id: I021577e331b7beb19796bd6f5465b867f6038974
>> Signed-off-by: Evan Quan <evan.quan at amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++++++----
>>  1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index ee537423af11..cb7f2efa9882 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3629,9 +3629,11 @@ static void
>> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
>>               /* update CGCG and CGLS override bits */
>>               if (def != data)
>>                       WREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE, data);
>> -             /* enable 3Dcgcg FSM(0x0020003f) */
>> +
>> +             /* enable 3Dcgcg FSM(0x0000363f) */
>>               def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
>> -             data = (0x2000 <<
>> RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>> +
>> +             data = (0x36 <<
>> +RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>>                       RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
>>               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
>>                       data |= (0x000F <<
>> RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>> @@ -3678,9 +3680,10 @@ static void
>> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>>               if (def != data)
>>                       WREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE, data);
>>
>> -             /* enable cgcg FSM(0x0020003F) */
>> +             /* enable cgcg FSM(0x0000363F) */
>>               def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
>> -             data = (0x2000 <<
>> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>> +
>> +             data = (0x36 <<
>> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>>                       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>>               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
>>                       data |= (0x000F <<
>> RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>> --
>> 2.18.0
>
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