[PATCH v2] drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega

[Michel Dänzer]

On 2018-07-12 04:09 PM, Harry Wentland wrote:
> The driver is expecting clock frequency in kHz, while SMU returns
> the values in 10kHz, which causes the bandwidth validation to fail
> 
> 4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
> only, which is only used by Vega. Make sure we multiply these values
> by 10 here, as we do for other ASICs as powerplay assigned them
> wrong. 4.19 has the proper fix in powerplay.
> 
> v2: Add Fixes tag
> 
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=107082

Bugzilla: https://bugs.freedesktop.org/107082

With that fixed,

Acked-by: Michel Dänzer <michel.daenzer at amd.com>


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Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer