[PATCH 2/2] drm/amdkfd: Call kfd2kgd.set_compute_idle
Alex Deucher
alexdeucher at gmail.com
Tue Jul 17 16:14:48 UTC 2018
On Mon, Jul 16, 2018 at 7:10 PM, Felix Kuehling <Felix.Kuehling at amd.com> wrote:
> User mode queue submissions don't go through KFD. Therefore we don't
> know exactly when compute is idle or not idle. We use the existence
> of user mode queues on a device as an approximation.
>
> register_process is called when the first queue of a process is
> created. Conversely unregister_process is called when the last queue
> is destroyed. The first process that is registered takes compute
> out of idle. The last process that is unregisters sets compute back
> to idle.
>
> Signed-off-by: Felix Kuehling <Felix.Kuehling at amd.com>
> Reviewed-by: Eric Huang <JinHuiEric.Huang at amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index ace94d6..ec0d62a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -782,7 +782,8 @@ static int register_process(struct device_queue_manager *dqm,
>
> retval = dqm->asic_ops.update_qpd(dqm, qpd);
>
> - dqm->processes_count++;
> + if (dqm->processes_count++ == 0)
> + dqm->dev->kfd2kgd->set_compute_idle(dqm->dev->kgd, false);
>
> dqm_unlock(dqm);
>
> @@ -805,7 +806,9 @@ static int unregister_process(struct device_queue_manager *dqm,
> if (qpd == cur->qpd) {
> list_del(&cur->list);
> kfree(cur);
> - dqm->processes_count--;
> + if (--dqm->processes_count == 0)
> + dqm->dev->kfd2kgd->set_compute_idle(
> + dqm->dev->kgd, true);
> goto out;
> }
> }
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
More information about the amd-gfx
mailing list