[PATCH 2/2] drm/amdgpu: patch the IBs for the second UVD instance v2

[James Zhu]

On 2018-07-25 07:05 AM, Christian König wrote:
> Patch the IBs for the second UVD instance so that userspace don't need
> to care about the instance they submit to.
>
> v2: use direct IB patching
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 27 +++++++++++++++++++++++++++
>   1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index db5f3d78ab12..0895b80fcd37 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1205,6 +1205,32 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
>   	return r;
>   }
>   
> +/**
> + * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
> + *
> + * @ring: the engine to test on
> + *
> + */
> +static int uvd_v7_0_ring_patch_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
> +{
> +	struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
> +	unsigned i;
> +
> +	/* No patching necessary for the first instance */
> +	if (!p->ring->me)
> +		return 0;
> +
> +	for (i = 0; i < ib->length_dw; i += 2) {
> +		uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
> +
> +		reg -= p->adev->reg_offset[UVD_HWIP][0][1];
> +		reg += p->adev->reg_offset[UVD_HWIP][1][1];
> +
> +		amdgpu_set_ib_value(p, ib_idx, i, reg);
> +	}
> +	return 0;
> +}
> +
>   /**
>    * uvd_v7_0_ring_emit_ib - execute indirect buffer
>    *
> @@ -1697,6 +1723,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
>   	.get_rptr = uvd_v7_0_ring_get_rptr,
>   	.get_wptr = uvd_v7_0_ring_get_wptr,
>   	.set_wptr = uvd_v7_0_ring_set_wptr,
> +	.patch_cs = uvd_v7_0_ring_patch_cs,
It should be .patch_cs_in_place. With this fix,

Reviewed-by: James Zhu <James.Zhu at amd.com>

James

>   	.emit_frame_size =
>   		6 + /* hdp invalidate */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +