[PATCH 1/2] drm/amd/pp: Make sure clock_voltage_limit_table on dc is valid

[Rex Zhu]

if vbios not set the max clock voltage limit table for DC mode,
Set the table as sama as the table for AC mode.

Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index d3649ce..f46d3be 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2503,6 +2503,11 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
 		smu7_patch_dependency_tables_with_leakage(hwmgr);
 		smu7_set_private_data_based_on_pptable_v0(hwmgr);
+		/* make sure dc limits are valid */
+		if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
+			(hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
+			hwmgr->dyn_state.max_clock_voltage_on_dc =
+					hwmgr->dyn_state.max_clock_voltage_on_ac;
 	}
 
 	/* Initalize Dynamic State Adjustment Rule Settings */
-- 
1.9.1