[PATCH 4/5] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu

[Quan, Evan]

Comment inline

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, June 05, 2018 1:22 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhu, Rex <Rex.Zhu at amd.com>
> Subject: [PATCH 4/5] drm/amd/pp: Add gfx pg support in smu through
> set_powergating_by_smu
> 
> gfx ip block can call set_powergating_by_smu to set gfx pg state if necessary.
> 
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 10 ++++------
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  4 ++--
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 17
> +++++++++++++++++
>  3 files changed, 23 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 818874b..50ba9c9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -5552,14 +5552,12 @@ static int gfx_v8_0_late_init(void *handle)  static
> void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device
> *adev,
>  						       bool enable)
>  {
> -	if ((adev->asic_type == CHIP_POLARIS11) ||
> +	if (((adev->asic_type == CHIP_POLARIS11) ||
>  	    (adev->asic_type == CHIP_POLARIS12) ||
> -	    (adev->asic_type == CHIP_VEGAM))
> +	    (adev->asic_type == CHIP_VEGAM)) &&
> +	    adev->powerplay.pp_funcs->set_powergating_by_smu)
>  		/* Send msg to SMU via Powerplay */
> -		amdgpu_device_ip_set_powergating_state(adev,
> -
> AMD_IP_BLOCK_TYPE_SMC,
> -						       enable ?
> -						       AMD_PG_STATE_GATE :
> AMD_PG_STATE_UNGATE);
> +		amdgpu_dpm_set_powergating_by_smu(adev,
> AMD_IP_BLOCK_TYPE_GFX,
> +enable);
> 
>  	WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE,
> enable ? 1 : 0);  } diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 377f536..85cf2f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct
> amdgpu_device *adev,
> 
> 	RENG_EXECUTE_ON_REG_UPDATE, 1);
>  		WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE,
> pctl1_reng_execute);
> 
> -		if (adev->powerplay.pp_funcs->powergate_mmhub)
> -			amdgpu_dpm_powergate_mmhub(adev);
> +		if (adev->powerplay.pp_funcs->set_powergating_by_smu)
> +			amdgpu_dpm_set_powergating_by_smu(adev,
> AMD_IP_BLOCK_TYPE_GMC, 0);
[Evan]  The third argument represents for "gate". So, it seems '1' is more suitable(although for mmhub it seems have no real effect).
> 
>  	} else {
>  		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 56dd4d9..e519cef 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1199,6 +1199,22 @@ static int pp_dpm_powergate_mmhub(void
> *handle)
>  	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
>  }
> 
> +static int pp_dpm_powergate_gfx(void *handle, bool gate) {
> +	struct amdgpu_device *adev = handle;
> +	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> +
> +	if (!hwmgr || !hwmgr->pm_en)
> +		return 0;
> +
> +	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
> +		pr_info("%s was not implemented.\n", __func__);
> +		return 0;
> +	}
> +
> +	return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); }
> +
>  static int pp_set_powergating_by_smu(void *handle,
>  				uint32_t block_type, bool gate)
>  {
> @@ -1216,6 +1232,7 @@ static int pp_set_powergating_by_smu(void
> *handle,
>  		pp_dpm_powergate_mmhub(handle);
>  		break;
>  	case AMD_IP_BLOCK_TYPE_GFX:
> +		ret = pp_dpm_powergate_gfx(handle, gate);
>  		break;
>  	default:
>  		break;
> --
> 1.9.1
> 
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