[PATCH] drm/amd/pp: Remove SAMU support in powerplay

Deucher, Alexander Alexander.Deucher at amd.com
Wed Jun 13 13:51:26 UTC 2018


Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Wednesday, June 13, 2018 3:34:05 AM
To: amd-gfx at lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Remove SAMU support in powerplay

As the SAMU ip was not supported in linux,
so delete the SAMU support in powerplay on
asics Bonarire/Hawwii/Tonga/Fiji/Polaris/vegam.

Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 .../amd/powerplay/hwmgr/smu7_clockpowergating.c    | 54 --------------
 .../amd/powerplay/hwmgr/smu7_clockpowergating.h    |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h   |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 -
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h         |  2 -
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c   | 35 ---------
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 74 -------------------
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  | 10 ---
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    | 86 ----------------------
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c    | 80 --------------------
 .../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c    | 85 ---------------------
 12 files changed, 430 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 6d72a56..4149562 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -39,13 +39,6 @@ static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
                         PPSMC_MSG_VCEDPM_Disable);
 }

-static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
-{
-       return smum_send_msg_to_smc(hwmgr, enable ?
-                       PPSMC_MSG_SAMUDPM_Enable :
-                       PPSMC_MSG_SAMUDPM_Disable);
-}
-
 static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 {
         if (!bgate)
@@ -60,13 +53,6 @@ static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
         return smu7_enable_disable_vce_dpm(hwmgr, !bgate);
 }

-static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-{
-       if (!bgate)
-               smum_update_smc_table(hwmgr, SMU_SAMU_TABLE);
-       return smu7_enable_disable_samu_dpm(hwmgr, !bgate);
-}
-
 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
 {
         if (phm_cf_want_uvd_power_gating(hwmgr))
@@ -107,35 +93,15 @@ static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
         return 0;
 }

-static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
-{
-       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-                       PHM_PlatformCaps_SamuPowerGating))
-               return smum_send_msg_to_smc(hwmgr,
-                               PPSMC_MSG_SAMPowerOFF);
-       return 0;
-}
-
-static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
-{
-       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-                       PHM_PlatformCaps_SamuPowerGating))
-               return smum_send_msg_to_smc(hwmgr,
-                               PPSMC_MSG_SAMPowerON);
-       return 0;
-}
-
 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
 {
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

         data->uvd_power_gated = false;
         data->vce_power_gated = false;
-       data->samu_power_gated = false;

         smu7_powerup_uvd(hwmgr);
         smu7_powerup_vce(hwmgr);
-       smu7_powerup_samu(hwmgr);

         return 0;
 }
@@ -195,26 +161,6 @@ void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
         }
 }

-int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
-{
-       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
-       if (data->samu_power_gated == bgate)
-               return 0;
-
-       data->samu_power_gated = bgate;
-
-       if (bgate) {
-               smu7_update_samu_dpm(hwmgr, true);
-               smu7_powerdown_samu(hwmgr);
-       } else {
-               smu7_powerup_samu(hwmgr);
-               smu7_update_samu_dpm(hwmgr, false);
-       }
-
-       return 0;
-}
-
 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
                                         const uint32_t *msg_id)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index 1ddce02..be7f66d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -29,7 +29,6 @@
 void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
 void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
-int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 11e1762..a338142 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4244,7 +4244,6 @@ static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)

         data->uvd_power_gated = false;
         data->vce_power_gated = false;
-       data->samu_power_gated = false;

         return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index c91e75d..3784ce6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -310,7 +310,6 @@ struct smu7_hwmgr {
         /* ---- Power Gating States ---- */
         bool                           uvd_power_gated;
         bool                           vce_power_gated;
-       bool                           samu_power_gated;
         bool                           need_long_memory_training;

         /* Application power optimization parameters */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index aadd6cb..339820d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -370,7 +370,6 @@ struct vega10_hwmgr {
         /* ---- Power Gating States ---- */
         bool                           uvd_power_gated;
         bool                           vce_power_gated;
-       bool                           samu_power_gated;
         bool                           need_long_memory_training;

         /* Internal settings to apply the application power optimization parameters */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 6c22ed9..89dfbf5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -29,7 +29,6 @@
 enum SMU_TABLE {
         SMU_UVD_TABLE = 0,
         SMU_VCE_TABLE,
-       SMU_SAMU_TABLE,
         SMU_BIF_TABLE,
 };

@@ -47,7 +46,6 @@ enum SMU_MEMBER {
         UcodeLoadStatus,
         UvdBootLevel,
         VceBootLevel,
-       SamuBootLevel,
         LowSclkInterruptThreshold,
         DRAM_LOG_ADDR_H,
         DRAM_LOG_ADDR_L,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 2d4ec8a..8cd21ac 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -1614,37 +1614,6 @@ static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
         return result;
 }

-static int ci_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-                                       SMU7_Discrete_DpmTable *table)
-{
-       int result = -EINVAL;
-       uint8_t count;
-       struct pp_atomctrl_clock_dividers_vi dividers;
-       struct phm_samu_clock_voltage_dependency_table *samu_table =
-                               hwmgr->dyn_state.samu_clock_voltage_dependency_table;
-
-       table->SamuBootLevel = 0;
-       table->SamuLevelCount = (uint8_t)(samu_table->count);
-
-       for (count = 0; count < table->SamuLevelCount; count++) {
-               table->SamuLevel[count].Frequency = samu_table->entries[count].samclk;
-               table->SamuLevel[count].MinVoltage = samu_table->entries[count].v * VOLTAGE_SCALE;
-               table->SamuLevel[count].MinPhases = 1;
-
-               /* retrieve divider value for VBIOS */
-               result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-                               table->SamuLevel[count].Frequency, &dividers);
-               PP_ASSERT_WITH_CODE((0 == result),
-                               "can not find divide id for samu clock", return result);
-
-               table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-               CONVERT_FROM_HOST_TO_SMC_US(table->SamuLevel[count].MinVoltage);
-       }
-       return result;
-}
-
 static int ci_populate_memory_timing_parameters(
                 struct pp_hwmgr *hwmgr,
                 uint32_t engine_clock,
@@ -2026,10 +1995,6 @@ static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
         PP_ASSERT_WITH_CODE(0 == result,
                 "Failed to initialize ACP Level!", return result);

-       result = ci_populate_smc_samu_level(hwmgr, table);
-       PP_ASSERT_WITH_CODE(0 == result,
-               "Failed to initialize SAMU Level!", return result);
-
         /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
         /* need to populate the  ARB settings for the initial state. */
         result = ci_program_memory_timing_parameters(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 53df940..18048f8 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -1503,44 +1503,6 @@ static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
         return result;
 }

-static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-               SMU73_Discrete_DpmTable *table)
-{
-       int result = -EINVAL;
-       uint8_t count;
-       struct pp_atomctrl_clock_dividers_vi dividers;
-       struct phm_ppt_v1_information *table_info =
-                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
-       struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-                       table_info->mm_dep_table;
-
-       table->SamuBootLevel = 0;
-       table->SamuLevelCount = (uint8_t)(mm_table->count);
-
-       for (count = 0; count < table->SamuLevelCount; count++) {
-               /* not sure whether we need evclk or not */
-               table->SamuLevel[count].MinVoltage = 0;
-               table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-               table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-                               VOLTAGE_SCALE) << VDDC_SHIFT;
-               table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-                               VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-               table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
-               /* retrieve divider value for VBIOS */
-               result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-                               table->SamuLevel[count].Frequency, &dividers);
-               PP_ASSERT_WITH_CODE((0 == result),
-                               "can not find divide id for samu clock", return result);
-
-               table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-       }
-       return result;
-}
-
 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
                 int32_t eng_clock, int32_t mem_clock,
                 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
@@ -2028,10 +1990,6 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
         PP_ASSERT_WITH_CODE(0 == result,
                         "Failed to initialize ACP Level!", return result);

-       result = fiji_populate_smc_samu_level(hwmgr, table);
-       PP_ASSERT_WITH_CODE(0 == result,
-                       "Failed to initialize SAMU Level!", return result);
-
         /* Since only the initial state is completely set up at this point
          * (the other states are just copies of the boot state) we only
          * need to populate the  ARB settings for the initial state.
@@ -2378,8 +2336,6 @@ static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
                         return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
                 case VceBootLevel:
                         return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
-               case SamuBootLevel:
-                       return offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
                 case LowSclkInterruptThreshold:
                         return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
                 }
@@ -2478,33 +2434,6 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
         return 0;
 }

-static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-{
-       struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-       uint32_t mm_boot_level_offset, mm_boot_level_value;
-
-
-       smu_data->smc_state_table.SamuBootLevel = 0;
-       mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-                               offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
-
-       mm_boot_level_offset /= 4;
-       mm_boot_level_offset *= 4;
-       mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset);
-       mm_boot_level_value &= 0xFFFFFF00;
-       mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
-       cgs_write_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
-       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-                       PHM_PlatformCaps_StablePState))
-               smum_send_msg_to_smc_with_parameter(hwmgr,
-                               PPSMC_MSG_SAMUDPM_SetEnabledMask,
-                               (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
-       return 0;
-}
-
 static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
 {
         switch (type) {
@@ -2514,9 +2443,6 @@ static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
         case SMU_VCE_TABLE:
                 fiji_update_vce_smc_table(hwmgr);
                 break;
-       case SMU_SAMU_TABLE:
-               fiji_update_samu_smc_table(hwmgr);
-               break;
         default:
                 break;
         }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 415f691..9299b93 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -1578,12 +1578,6 @@ static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
         return 0;
 }

-static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-       SMU71_Discrete_DpmTable *table)
-{
-       return 0;
-}
-
 static int iceland_populate_memory_timing_parameters(
                 struct pp_hwmgr *hwmgr,
                 uint32_t engine_clock,
@@ -1992,10 +1986,6 @@ static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
         PP_ASSERT_WITH_CODE(0 == result,
                 "Failed to initialize ACP Level!", return result;);

-       result = iceland_populate_smc_samu_level(hwmgr, table);
-       PP_ASSERT_WITH_CODE(0 == result,
-               "Failed to initialize SAMU Level!", return result;);
-
         /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
         /* need to populate the  ARB settings for the initial state. */
         result = iceland_program_memory_timing_parameters(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index a8c6524..a4ce199 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -1337,55 +1337,6 @@ static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
         return result;
 }

-
-static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-               SMU74_Discrete_DpmTable *table)
-{
-       int result = -EINVAL;
-       uint8_t count;
-       struct pp_atomctrl_clock_dividers_vi dividers;
-       struct phm_ppt_v1_information *table_info =
-                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
-       struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-                       table_info->mm_dep_table;
-       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-       uint32_t vddci;
-
-       table->SamuBootLevel = 0;
-       table->SamuLevelCount = (uint8_t)(mm_table->count);
-
-       for (count = 0; count < table->SamuLevelCount; count++) {
-               /* not sure whether we need evclk or not */
-               table->SamuLevel[count].MinVoltage = 0;
-               table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-               table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-                               VOLTAGE_SCALE) << VDDC_SHIFT;
-
-               if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-                       vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
-                                               mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-               else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
-                       vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
-               else
-                       vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-
-               table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-               table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
-               /* retrieve divider value for VBIOS */
-               result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-                               table->SamuLevel[count].Frequency, &dividers);
-               PP_ASSERT_WITH_CODE((0 == result),
-                               "can not find divide id for samu clock", return result);
-
-               table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-       }
-       return result;
-}
-
 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
                 int32_t eng_clock, int32_t mem_clock,
                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
@@ -1865,10 +1816,6 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
         PP_ASSERT_WITH_CODE(0 == result,
                         "Failed to initialize VCE Level!", return result);

-       result = polaris10_populate_smc_samu_level(hwmgr, table);
-       PP_ASSERT_WITH_CODE(0 == result,
-                       "Failed to initialize SAMU Level!", return result);
-
         /* Since only the initial state is completely set up at this point
          * (the other states are just copies of the boot state) we only
          * need to populate the  ARB settings for the initial state.
@@ -2222,34 +2169,6 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
         return 0;
 }

-static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-{
-       struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-       uint32_t mm_boot_level_offset, mm_boot_level_value;
-
-
-       smu_data->smc_state_table.SamuBootLevel = 0;
-       mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-                               offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
-
-       mm_boot_level_offset /= 4;
-       mm_boot_level_offset *= 4;
-       mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset);
-       mm_boot_level_value &= 0xFFFFFF00;
-       mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
-       cgs_write_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
-       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-                       PHM_PlatformCaps_StablePState))
-               smum_send_msg_to_smc_with_parameter(hwmgr,
-                               PPSMC_MSG_SAMUDPM_SetEnabledMask,
-                               (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
-       return 0;
-}
-
-
 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
 {
         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
@@ -2276,9 +2195,6 @@ static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
         case SMU_VCE_TABLE:
                 polaris10_update_vce_smc_table(hwmgr);
                 break;
-       case SMU_SAMU_TABLE:
-               polaris10_update_samu_smc_table(hwmgr);
-               break;
         case SMU_BIF_TABLE:
                 polaris10_update_bif_smc_table(hwmgr);
         default:
@@ -2357,8 +2273,6 @@ static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
                         return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
                 case VceBootLevel:
                         return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
-               case SamuBootLevel:
-                       return offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
                 case LowSclkInterruptThreshold:
                         return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
                 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 782b19f..7dabc6c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -1443,51 +1443,6 @@ static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
         return result;
 }

-static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-               SMU72_Discrete_DpmTable *table)
-{
-       int result = 0;
-       uint8_t count;
-       pp_atomctrl_clock_dividers_vi dividers;
-       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-       struct phm_ppt_v1_information *pptable_info =
-                            (struct phm_ppt_v1_information *)(hwmgr->pptable);
-       phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-                                                   pptable_info->mm_dep_table;
-
-       table->SamuBootLevel = 0;
-       table->SamuLevelCount = (uint8_t) (mm_table->count);
-
-       for (count = 0; count < table->SamuLevelCount; count++) {
-               /* not sure whether we need evclk or not */
-               table->SamuLevel[count].Frequency =
-                       pptable_info->mm_dep_table->entries[count].samclock;
-               table->SamuLevel[count].MinVoltage.Vddc =
-                       phm_get_voltage_index(pptable_info->vddc_lookup_table,
-                               mm_table->entries[count].vddc);
-               table->SamuLevel[count].MinVoltage.VddGfx =
-                       (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
-                       phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
-                               mm_table->entries[count].vddgfx) : 0;
-               table->SamuLevel[count].MinVoltage.Vddci =
-                       phm_get_voltage_id(&data->vddci_voltage_table,
-                               mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-               table->SamuLevel[count].MinVoltage.Phases = 1;
-
-               /* retrieve divider value for VBIOS */
-               result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-                                       table->SamuLevel[count].Frequency, &dividers);
-               PP_ASSERT_WITH_CODE((!result),
-                       "can not find divide id for samu clock", return result);
-
-               table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-       }
-
-       return result;
-}
-
 static int tonga_populate_memory_timing_parameters(
                 struct pp_hwmgr *hwmgr,
                 uint32_t engine_clock,
@@ -2323,10 +2278,6 @@ static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
         PP_ASSERT_WITH_CODE(!result,
                 "Failed to initialize ACP Level !", return result);

-       result = tonga_populate_smc_samu_level(hwmgr, table);
-       PP_ASSERT_WITH_CODE(!result,
-               "Failed to initialize SAMU Level !", return result);
-
         /* Since only the initial state is completely set up at this
         * point (the other states are just copies of the boot state) we only
         * need to populate the  ARB settings for the initial state.
@@ -2673,8 +2624,6 @@ static uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
                         return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
                 case VceBootLevel:
                         return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
-               case SamuBootLevel:
-                       return offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
                 case LowSclkInterruptThreshold:
                         return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
                 }
@@ -2773,32 +2722,6 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
         return 0;
 }

-static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-{
-       struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-       uint32_t mm_boot_level_offset, mm_boot_level_value;
-
-       smu_data->smc_state_table.SamuBootLevel = 0;
-       mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-                               offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
-
-       mm_boot_level_offset /= 4;
-       mm_boot_level_offset *= 4;
-       mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset);
-       mm_boot_level_value &= 0xFFFFFF00;
-       mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
-       cgs_write_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
-       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-                       PHM_PlatformCaps_StablePState))
-               smum_send_msg_to_smc_with_parameter(hwmgr,
-                               PPSMC_MSG_SAMUDPM_SetEnabledMask,
-                               (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
-       return 0;
-}
-
 static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
 {
         switch (type) {
@@ -2808,9 +2731,6 @@ static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
         case SMU_VCE_TABLE:
                 tonga_update_vce_smc_table(hwmgr);
                 break;
-       case SMU_SAMU_TABLE:
-               tonga_update_samu_smc_table(hwmgr);
-               break;
         default:
                 break;
         }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
index 2de4895..57420d7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
@@ -393,34 +393,6 @@ static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
         return 0;
 }

-static int vegam_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-{
-       struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
-       uint32_t mm_boot_level_offset, mm_boot_level_value;
-
-
-       smu_data->smc_state_table.SamuBootLevel = 0;
-       mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-                               offsetof(SMU75_Discrete_DpmTable, SamuBootLevel);
-
-       mm_boot_level_offset /= 4;
-       mm_boot_level_offset *= 4;
-       mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset);
-       mm_boot_level_value &= 0xFFFFFF00;
-       mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
-       cgs_write_ind_register(hwmgr->device,
-                       CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
-       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-                       PHM_PlatformCaps_StablePState))
-               smum_send_msg_to_smc_with_parameter(hwmgr,
-                               PPSMC_MSG_SAMUDPM_SetEnabledMask,
-                               (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
-       return 0;
-}
-
-
 static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
 {
         struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
@@ -447,9 +419,6 @@ static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
         case SMU_VCE_TABLE:
                 vegam_update_vce_smc_table(hwmgr);
                 break;
-       case SMU_SAMU_TABLE:
-               vegam_update_samu_smc_table(hwmgr);
-               break;
         case SMU_BIF_TABLE:
                 vegam_update_bif_smc_table(hwmgr);
                 break;
@@ -1281,54 +1250,6 @@ static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
         return result;
 }

-static int vegam_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-               SMU75_Discrete_DpmTable *table)
-{
-       int result = -EINVAL;
-       uint8_t count;
-       struct pp_atomctrl_clock_dividers_vi dividers;
-       struct phm_ppt_v1_information *table_info =
-                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
-       struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-                       table_info->mm_dep_table;
-       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-       uint32_t vddci;
-
-       table->SamuBootLevel = 0;
-       table->SamuLevelCount = (uint8_t)(mm_table->count);
-
-       for (count = 0; count < table->SamuLevelCount; count++) {
-               /* not sure whether we need evclk or not */
-               table->SamuLevel[count].MinVoltage = 0;
-               table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-               table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-                               VOLTAGE_SCALE) << VDDC_SHIFT;
-
-               if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-                       vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
-                                               mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-               else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
-                       vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
-               else
-                       vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-
-               table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-               table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
-               /* retrieve divider value for VBIOS */
-               result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-                               table->SamuLevel[count].Frequency, &dividers);
-               PP_ASSERT_WITH_CODE((0 == result),
-                               "can not find divide id for samu clock", return result);
-
-               table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-               CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-       }
-       return result;
-}
-
 static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
                 int32_t eng_clock, int32_t mem_clock,
                 SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
@@ -2062,10 +1983,6 @@ static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
         PP_ASSERT_WITH_CODE(!result,
                         "Failed to initialize VCE Level!", return result);

-       result = vegam_populate_smc_samu_level(hwmgr, table);
-       PP_ASSERT_WITH_CODE(!result,
-                       "Failed to initialize SAMU Level!", return result);
-
         /* Since only the initial state is completely set up at this point
          * (the other states are just copies of the boot state) we only
          * need to populate the  ARB settings for the initial state.
@@ -2273,8 +2190,6 @@ static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)
                         return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
                 case VceBootLevel:
                         return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
-               case SamuBootLevel:
-                       return offsetof(SMU75_Discrete_DpmTable, SamuBootLevel);
                 case LowSclkInterruptThreshold:
                         return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold);
                 }
--
1.9.1

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