[PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used

[Zhang, Jerry]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of
> Christian K?nig
> Sent: Friday, June 15, 2018 15:09
> To: Zhou, David(ChunMing) <David1.Zhou at amd.com>; amd-
> gfx at lists.freedesktop.org
> Cc: Olsak, Marek <Marek.Olsak at amd.com>; Ryan, Sean <Sean.Ryan at amd.com>
> Subject: Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as
> windows used
> 
> Am 15.06.2018 um 08:45 schrieb Chunming Zhou:
> > PAGE_SIZE for start_alignment is far much than hw requirement, And
> > now, update to expereince value from window side.
> >
> > Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
> > Signed-off-by: Chunming Zhou <david1.zhou at amd.com>
> 
> Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Junwei Zhang <Jerry.Zhang at amd.com>

BTW, any issue it fixes?

Jerry

> 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 ++++++++++++++---------
> -----
> >   1 file changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index 392dd24e83f5..d041dddaad0c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
> void *data, struct drm_file
> >   			type = AMD_IP_BLOCK_TYPE_GFX;
> >   			for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> >   				ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0)
> << i);
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > -			ib_size_alignment = 8;
> > +			ib_start_alignment = 32;
> > +			ib_size_alignment = 32;
> >   			break;
> >   		case AMDGPU_HW_IP_COMPUTE:
> >   			type = AMD_IP_BLOCK_TYPE_GFX;
> >   			for (i = 0; i < adev->gfx.num_compute_rings; i++)
> >   				ring_mask |= ((adev->gfx.compute_ring[i].ready ?
> 1 : 0) << i);
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > -			ib_size_alignment = 8;
> > +			ib_start_alignment = 32;
> > +			ib_size_alignment = 32;
> >   			break;
> >   		case AMDGPU_HW_IP_DMA:
> >   			type = AMD_IP_BLOCK_TYPE_SDMA;
> >   			for (i = 0; i < adev->sdma.num_instances; i++)
> >   				ring_mask |= ((adev-
> >sdma.instance[i].ring.ready ? 1 : 0) << i);
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > -			ib_size_alignment = 1;
> > +			ib_start_alignment = 256;
> > +			ib_size_alignment = 4;
> >   			break;
> >   		case AMDGPU_HW_IP_UVD:
> >   			type = AMD_IP_BLOCK_TYPE_UVD;
> >   			for (i = 0; i < adev->uvd.num_uvd_inst; i++)
> >   				ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0)
> << i);
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > -			ib_size_alignment = 16;
> > +			ib_start_alignment = 64;
> > +			ib_size_alignment = 64;
> >   			break;
> >   		case AMDGPU_HW_IP_VCE:
> >   			type = AMD_IP_BLOCK_TYPE_VCE;
> >   			for (i = 0; i < adev->vce.num_rings; i++)
> >   				ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) <<
> i);
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > +			ib_start_alignment = 4;
> >   			ib_size_alignment = 1;
> >   			break;
> >   		case AMDGPU_HW_IP_UVD_ENC:
> > @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
> void *data, struct drm_file
> >   					ring_mask |=
> >   					((adev->uvd.inst[i].ring_enc[j].ready ? 1 :
> 0) <<
> >   					(j + i * adev->uvd.num_enc_rings));
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > -			ib_size_alignment = 1;
> > +			ib_start_alignment = 64;
> > +			ib_size_alignment = 64;
> >   			break;
> >   		case AMDGPU_HW_IP_VCN_DEC:
> >   			type = AMD_IP_BLOCK_TYPE_VCN;
> >   			ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > +			ib_start_alignment = 16;
> >   			ib_size_alignment = 16;
> >   			break;
> >   		case AMDGPU_HW_IP_VCN_ENC:
> >   			type = AMD_IP_BLOCK_TYPE_VCN;
> >   			for (i = 0; i < adev->vcn.num_enc_rings; i++)
> >   				ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0)
> << i);
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > +			ib_start_alignment = 64;
> >   			ib_size_alignment = 1;
> >   			break;
> >   		case AMDGPU_HW_IP_VCN_JPEG:
> >   			type = AMD_IP_BLOCK_TYPE_VCN;
> >   			ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
> > -			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > +			ib_start_alignment = 16;
> >   			ib_size_alignment = 16;
> >   			break;
> >   		default:
> 
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