[PATCH 3/5] drm/amd/pp: Memory Latency is always 25us on Vega10

[Alex Deucher]

On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> Also use the tolerable latency defined in Display
> to find lowest MCLK frequency when disable mclk switch

This should probably be two patches?  One to fix the memory latency,
and one to switch the tolerable latency for display.  With that fixed:
Acked-by: Alex Deucher <alexander.deucher at amd.com>

>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ++--------------------
>  1 file changed, 2 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 6057b59..198c7ed 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -55,12 +55,6 @@
>
>  static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
>
> -#define MEM_FREQ_LOW_LATENCY        25000
> -#define MEM_FREQ_HIGH_LATENCY       80000
> -#define MEM_LATENCY_HIGH            245
> -#define MEM_LATENCY_LOW             35
> -#define MEM_LATENCY_ERR             0xFFFF
> -
>  #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
>  #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
>
> @@ -3223,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
>                 /* Find the lowest MCLK frequency that is within
>                  * the tolerable latency defined in DAL
>                  */
> -               latency = 0;
> +               latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
>                 for (i = 0; i < data->mclk_latency_table.count; i++) {
>                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
>                                 (data->mclk_latency_table.entries[i].frequency >=
> @@ -4074,18 +4068,6 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
>
>  }
>
> -static uint32_t vega10_get_mem_latency(struct pp_hwmgr *hwmgr,
> -               uint32_t clock)
> -{
> -       if (clock >= MEM_FREQ_LOW_LATENCY &&
> -                       clock < MEM_FREQ_HIGH_LATENCY)
> -               return MEM_LATENCY_HIGH;
> -       else if (clock >= MEM_FREQ_HIGH_LATENCY)
> -               return MEM_LATENCY_LOW;
> -       else
> -               return MEM_LATENCY_ERR;
> -}
> -
>  static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
>                 struct pp_clock_levels_with_latency *clocks)
>  {
> @@ -4107,9 +4089,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
>                                         dep_table->entries[i].clk * 10;
>                         clocks->data[clocks->num_levels].latency_in_us =
>                         data->mclk_latency_table.entries
> -                       [data->mclk_latency_table.count].latency =
> -                                       vega10_get_mem_latency(hwmgr,
> -                                               dep_table->entries[i].clk);
> +                       [data->mclk_latency_table.count].latency = 25;
>                         clocks->num_levels++;
>                         data->mclk_latency_table.count++;
>                 }
> --
> 1.9.1
>
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