[PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

[Harry Wentland]

On 2018-06-18 07:18 AM, Rex Zhu wrote:
> Display component can get tru max_displ_clk_in_khz instand of hardcode
> 
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Mikita has pretty much the same patch (part of the DC patchset going out tomorrow) and did the *10 on our end. I prefer your version, though, as that multiplication should probably come from powerplay. Haven't had a ton of time to look at this patchset closely today but will do so tomorrow with Mikita and get back to you.

Harry

> ---
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 45 +++++++++++++++++++++-
>  1 file changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 5a33461..37f6a5f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> @@ -261,6 +261,33 @@ static void pp_to_dc_clock_levels_with_latency(
>  	}
>  }
>  
> +static void pp_to_dc_clock_levels_with_voltage(
> +		const struct pp_clock_levels_with_voltage *pp_clks,
> +		struct dm_pp_clock_levels_with_voltage *clk_level_info,
> +		enum dm_pp_clock_type dc_clk_type)
> +{
> +	uint32_t i;
> +
> +	if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
> +		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
> +				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
> +				pp_clks->num_levels,
> +				DM_PP_MAX_CLOCK_LEVELS);
> +
> +		clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
> +	} else
> +		clk_level_info->num_levels = pp_clks->num_levels;
> +
> +	DRM_DEBUG("DM_PPLIB: values for %s clock\n",
> +			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
> +
> +	for (i = 0; i < clk_level_info->num_levels; i++) {
> +		DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
> +		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
> +		clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
> +	}
> +}
> +
>  bool dm_pp_get_clock_levels_by_type(
>  		const struct dc_context *ctx,
>  		enum dm_pp_clock_type clk_type,
> @@ -361,8 +388,22 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
>  	enum dm_pp_clock_type clk_type,
>  	struct dm_pp_clock_levels_with_voltage *clk_level_info)
>  {
> -	/* TODO: to be implemented */
> -	return false;
> +	struct amdgpu_device *adev = ctx->driver_context;
> +	void *pp_handle = adev->powerplay.pp_handle;
> +	struct pp_clock_levels_with_voltage pp_clks = { 0 };
> +	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> +
> +	if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
> +		return false;
> +
> +	if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
> +						     dc_to_pp_clock_type(clk_type),
> +						     &pp_clks))
> +		return false;
> +
> +	pp_to_dc_clock_levels_with_voltage(&pp_clks, clk_level_info, clk_type);
> +
> +	return true;
>  }
>  
>  bool dm_pp_notify_wm_clock_changes(
>